Texas Instruments TDES9640RURT

Overview

TDES9640RURT from Texas Instruments is a V3Link deserializer hub that aggregates up to four 7.55 Gbps sensor streams into dual MIPI CSI-2 D-PHY/C-PHY outputs and one D-PHY replication port, supporting 8MP+ imaging systems over coaxial or STP cabling with Power-over-Coax (PoC). It operates across -20°C to 85°C and enables ultra-high-resolution machine vision and surveillance camera systems.

For engineers reviewing the TDES9640RURT datasheet, TDES9640RURT pinout, TDES9640RURT application, or TDES9640RURT equivalent, key selection criteria include its quad-channel V3Link RX capability, configurable MIPI D-PHY v2.1/C-PHY v1.1 output ports, VC-ID remapping support, frozen frame detection, and PoC-enabled single-cable architecture for compact sensor modules.

Technical Context

The TDES9640RURT implements a V3Link Enhanced Vision receiver with forward channel data rates of 7.55/3.775/1.8875 Gbps and a 47.1875 Mbps bidirectional control channel. It integrates automatic receiver equalization and supports both MIPI D-PHY v2.1 (up to 2.5 Gbps/lane) and C-PHY v1.1 (up to 5.7 Gbps/trio) on each of two primary output ports.

It provides three CSI-2 ports: two full-function D-PHY/C-PHY outputs and one D-PHY-only replication port. The device supports 16 virtual channels with programmable VC-ID remapping, enabling multi-sensor stream differentiation and flexible input-to-output routing in aggregation or replication topologies.

Key Specifications

Pinout & Package

VQFNP (RUR) package, 88-pin, 12.00 mm × 12.00 mm body size, 0.5 mm pitch, 0.9 mm max height, moisture sensitivity level 3 (260°C peak reflow, 168 hr floor life).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar deserializer hub applications.

Compared with TSER9615 (a serializer) and TDES954 (a lower-bandwidth deserializer), the TDES9640RURT uniquely delivers 7.55 Gbps aggregation, dual-mode MIPI output, and VC-ID remapping - making it the only option for 8MP+ multi-sensor systems requiring C-PHY compatibility or replication port functionality.

Availability

TDES9640RURT is available at Aetrix Electronics and suitable for machine vision systems, video surveillance infrastructure, and industrial robotics requiring stable component supply, long-term lifecycle assurance, and production-ready packaging (250-unit SMALL T&R reels).

Supply support for TDES9640RURT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in high-speed interface, imaging, and industrial communication technologies.

The TDES9640RURT belongs to TI's V3Link Enhanced Vision product line, designed specifically for ultra-high-resolution, multi-sensor camera systems in automotive-adjacent industrial applications where cable length, EMI immunity, and power efficiency are critical.

FAQ

What is the maximum supported data rate for each V3Link input channel on the TDES9640RURT?

The TDES9640RURT supports three forward channel data rates: 7.55 Gbps, 3.775 Gbps, and 1.8875 Gbps per V3Link RX lane. Its full 7.55 Gbps capability enables aggregation of 8MP+ image sensors. This rate is maintained across all four inputs simultaneously, and the device automatically adapts to the line rate negotiated with upstream serializers like the TSER9615 or TSER4905. The TDES9640RURT does not perform rate conversion between input and output domains.

Does the TDES9640RURT support both MIPI D-PHY and C-PHY output protocols on the same physical port?

Yes, the TDES9640RURT supports either MIPI D-PHY v2.1 or C-PHY v1.1 on each of its two primary CSI-2 output ports (CSI0 and CSI1), but not simultaneously on the same port. Configuration is done via register settings at initialization. CSI Port 2 is D-PHY-only and cannot be configured for C-PHY. The TDES9640RURT's flexibility allows direct interfacing with SoCs supporting either PHY standard without external protocol translation.

How many virtual channels does the TDES9640RURT support, and can their IDs be remapped?

The TDES9640RURT supports up to 16 virtual channels with full VC-ID remapping capability. Each incoming V3Link stream can be assigned a unique VC-ID, and those IDs can be dynamically reassigned at the output ports to match downstream processor expectations. This feature is implemented in hardware and enables seamless integration of heterogeneous sensors - such as RGB, IR, and depth - into a unified CSI-2 pipeline. The TDES9640RURT uses this remapping to maintain stream identity across aggregation and replication paths.

What is the purpose of the CMLOUT ports on the TDES9640RURT?

The TDES9640RURT features four CMLOUT ports that replicate the raw V3Link RX data from each of its four input channels. These outputs are intended to drive additional deserializers in daisy-chain or hierarchical topologies - for example, feeding a secondary TDES9640RURT or compatible device without requiring retiming or buffering. Each CMLOUT operates at the same line rate as its source RX port and preserves embedded control channel information, enabling scalable multi-hop camera link architectures. The TDES9640RURT maintains signal integrity on CMLOUTs via on-die termination and slew-rate control.

Is Power-over-Coax (PoC) supported by the TDES9640RURT, and how is it implemented?

Yes, the TDES9640RURT supports Power-over-Coax (PoC) as part of the V3Link Enhanced Vision standard. It receives DC power over the same coaxial or shielded twisted-pair cable used for high-speed data transmission, eliminating the need for separate power wiring at the sensor module. PoC implementation complies with TI's V3Link specification and works in conjunction with compatible serializers like the TSER9615. The TDES9640RURT includes internal PoC extraction circuitry and fault protection, and its power management supports low-power sleep mode with GPIO-state retention while maintaining PoC link integrity.