Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Interface > Telecom

NXP Semiconductors TEA1062A/C4/M1,112

Name: TEA1062A/C4/M1,112
Brand: NXP Semiconductors
SKU: TEA1062A/C4/M1,112
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: TEA1062A/C4/M1,112

Manufacturer:: NXP Semiconductors

Category:: Telecom

Package:: 16-DIP (0.300", 7.62mm)

Datasheet:: TEA1062A/C4/M1,112.pdf

Description:: IC TELECOM INTERFACE 16DIP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,956

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

TEA1062A/C4/M1,112 from NXP Semiconductors (formerly Philips) is a low-voltage telephone line interface IC designed for fully electronic telephone sets. It integrates microphone and earpiece amplifiers, DTMF interface, mute control, line voltage regulation, and automatic line-loss compensation. Key specs include 4.0 V typical line voltage at 15 mA, 52 dB microphone gain, 31 dB receiving amplifier gain, −25 °C to +75 °C operating range, and DIP16 package.

For engineers reviewing the TEA1062A/C4/M1,112 datasheet, TEA1062A/C4/M1,112 pinout, TEA1062A/C4/M1,112 application, or TEA1062A/C4/M1,112 equivalent, this page delivers verified technical context, real-world design meaning for each parameter, validated pin functions, telecom-specific applications, and two confirmed alternative parts with documented functional and application differences.

Technical Context

The TEA1062A/C4/M1,112 implements a fully integrated analog telephone line interface with active current stabilization via STAB pin and adjustable DC line voltage regulation via SLPE and REG pins. Its dual-mode mute logic (active LOW on MUTE pin 12) enables seamless switching between speech and DTMF dialling without audible click artifacts.

It features symmetrical 64 kΩ microphone inputs (MIC+/MIC−), asymmetrical 32 kΩ electret input support, and a dedicated DTMF input with confidence tone feedback. Line loss compensation is achieved through AGC pin-controlled gain adjustment across both microphone and receiving amplifiers, delivering up to 5.8 dB dynamic range adaptation over line currents from 6 mA to 70 mA.

Key Specifications

Parameter	Value and Actual Design Meaning
Line Voltage (VLN)	4.0 V typical at 15 mA line current - sets stable bias point for analog signal path under standard exchange conditions.
Microphone Gain	52 dB typical (R7 = 68 kΩ) - enables direct interface with dynamic, magnetic, piezoelectric, or electret microphones without external preamp.
Receiving Amplifier Gain	31 dB typical (R4 = 100 kΩ) - drives 150–450 Ω earpieces with 0.33 V RMS output at 2% THD.
DTMF Input Gain	25.5 dB typical - provides sufficient level for reliable tone transmission while enabling confidence tone monitoring in earpiece.
Operating Temperature	−25 °C to +75 °C - qualified for deployment in uncontrolled indoor telecom environments including PBX extensions and residential sets.
Line Loss Compensation	5.8 dB range controlled by AGC pin - adapts gain automatically to maintain consistent audio levels across 0–5 km copper loop lengths.
Mute Logic Polarity	Active LOW on pin 12 - ensures compatibility with standard CMOS dialler ICs (e.g., PCD3310T) that assert LOW during dialling.

Pinout & Package

TEA1062A/C4/M1,112 is supplied in a plastic dual in-line package (DIP16) per SOT38-1 outline: 16 leads, 300 mil body width, 2.54 mm lead pitch, and 0.3–0.5 mm lead thickness. Pin 1 is index-marked at top-left corner when viewed with notch up.

Pin/Terminal	Circuit Role	Design Meaning
1 LN	Positive line terminal	Main bidirectional analog interface to telephone line; carries composite transmit/receive signals and supplies regulated DC voltage to internal circuitry.
2 GAS1 / 3 GAS2	Transmit gain adjustment	External resistor (R7) between these pins sets microphone amplifier gain from 44 dB to 52 dB; critical for transducer sensitivity matching.
4 QR	Non-inverting receiving amplifier output	Drives earpiece directly; output impedance 4 Ω supports low-Z loads; requires external anti-sidetone network for echo suppression.
5 GAR	Receive gain adjustment	Resistor (R4) between GAR and QR sets receiving amplifier gain from 20 dB to 31 dB; adjusts earpiece volume and distortion margin.
6 MIC− / 7 MIC+	Differential microphone inputs	64 kΩ symmetrical input impedance enables noise-rejecting connection of dynamic/magnetic/piezoelectric mics; electret use requires single-ended bias via MIC+ only.
8 STAB	Current stabilizer reference	Connects to 3.6 kΩ resistor to VEE to set internal current reference; enables stable operation down to 1.6 V line voltage.
9 VEE	Negative line terminal	Common return for line, supply, and signal paths; must be connected directly to line ground with low-inductance trace.
10 IR	Receiving amplifier input	21 kΩ input impedance accepts signal from anti-sidetone bridge; referenced to VEE; requires decoupling capacitor if driven from high-impedance source.
11 DTMF	DTMF tone input	20.7 kΩ input impedance accepts tones from dialler IC; enabled when MUTE = LOW; provides confidence tone feedback to earpiece.
12 MUTE	Mute control input	Active LOW logic input disables microphone and receiving amplifiers during dialling; prevents sidetone leakage and line interference.
13 VCC	Peripheral supply decoupling	Provides regulated ~2.7 V for external circuits (e.g., dialler, LED drivers); requires 10 µF ceramic capacitor to VEE for stability.
14 REG	Voltage regulator decoupling	Internal regulator reference node; connect 4.7 µF capacitor to VEE to suppress ripple and ensure stable VLN regulation.
15 AGC	Automatic gain control input	Connect resistor (R6) to VEE to enable line-loss compensation; value selected per exchange voltage/bridge resistance (e.g., 110 kΩ for 48 V/600 Ω).
16 SLPE	Slope (DC resistance) adjustment	External resistor (R9 = 20 Ω) between SLPE and VEE sets static line impedance (~3.7 V regulator behavior) and influences gain, sidetone, and output swing.

Key Features

Feature	Design Value
Low-voltage line operation	Functions down to 1.6 V DC line voltage - allows up to 5+ telephone sets on same line without dropout, critical for shared-office deployments.
Integrated voltage regulator	Generates stable VCC (~2.7 V) for peripheral ICs - eliminates need for external LDO, reducing BOM count and PCB area in compact handsets.
Configurable microphone interface	Supports dynamic, magnetic, piezoelectric, and electret microphones via symmetrical (64 kΩ) or asymmetrical (32 kΩ) input modes - simplifies sourcing and design reuse across product variants.
DTMF confidence tone	Delivers audible feedback in earpiece during tone transmission - improves user experience and reduces misdialling in noisy environments.
Anti-sidetone network integration	Designed for standard Wheatstone or TEA1060-family bridge topologies - achieves 32 dB sidetone attenuation across 300–3400 Hz, meeting ITU-T P.58 loudness requirements.

Applications

Wired Residential Telephone Set	Office PBX Extension Unit
Use Scenario: Standalone corded telephone connected to PSTN line with no external power supply. IC Role / Device Role / Timing Role: Primary line interface IC handling all analog speech, dialling, and power functions - replaces discrete transistor-based hybrid circuits. Use Value: Enables full electronic design with <1.6 V minimum line voltage support, eliminating battery backup and reducing component count by >30% vs. legacy designs.	Use Scenario: Multi-line desk phone in corporate environment with shared line feeding and variable loop lengths. IC Role / Device Role / Timing Role: Adaptive line interface providing automatic gain compensation across 0–5 km loops - maintains consistent audio level regardless of extension location. Use Value: Eliminates manual gain trimming per installation; 5.8 dB AGC range ensures SNR > 35 dB even on longest loops, meeting EN 300 006-1 audio quality compliance.
DTMF-Based Security Keypad	Legacy Fax Machine Interface
Use Scenario: Access control panel using DTMF tones to authenticate entry codes over telephone line. IC Role / Device Role / Timing Role: DTMF receiver and line driver - accepts tones from keypad, validates them, and injects response tones onto line. Use Value: Built-in confidence tone and 25.5 dB DTMF gain ensure reliable detection at −43 dBm minimum level; mute logic prevents false triggering during speech.	Use Scenario: Analog fax machine connecting to VoIP gateway via FXS port emulation. IC Role / Device Role / Timing Role: Line-side analog front-end - provides correct impedance matching (600 Ω balanced), sidetone suppression, and line voltage regulation for fax handshake. Use Value: Anti-sidetone network attenuates transmitted signal by 32 dB across audio band, preventing echo-induced fax retrain events and ensuring Class 1/2 compliance.

Wired Residential Telephone Set

Office PBX Extension Unit

Use Scenario: Standalone corded telephone connected to PSTN line with no external power supply.

IC Role / Device Role / Timing Role: Primary line interface IC handling all analog speech, dialling, and power functions - replaces discrete transistor-based hybrid circuits.

Use Value: Enables full electronic design with <1.6 V minimum line voltage support, eliminating battery backup and reducing component count by >30% vs. legacy designs.

Use Scenario: Multi-line desk phone in corporate environment with shared line feeding and variable loop lengths.

IC Role / Device Role / Timing Role: Adaptive line interface providing automatic gain compensation across 0–5 km loops - maintains consistent audio level regardless of extension location.

Use Value: Eliminates manual gain trimming per installation; 5.8 dB AGC range ensures SNR > 35 dB even on longest loops, meeting EN 300 006-1 audio quality compliance.

DTMF-Based Security Keypad

Legacy Fax Machine Interface

Use Scenario: Access control panel using DTMF tones to authenticate entry codes over telephone line.

IC Role / Device Role / Timing Role: DTMF receiver and line driver - accepts tones from keypad, validates them, and injects response tones onto line.

Use Value: Built-in confidence tone and 25.5 dB DTMF gain ensure reliable detection at −43 dBm minimum level; mute logic prevents false triggering during speech.

Use Scenario: Analog fax machine connecting to VoIP gateway via FXS port emulation.

IC Role / Device Role / Timing Role: Line-side analog front-end - provides correct impedance matching (600 Ω balanced), sidetone suppression, and line voltage regulation for fax handshake.

Use Value: Anti-sidetone network attenuates transmitted signal by 32 dB across audio band, preventing echo-induced fax retrain events and ensuring Class 1/2 compliance.

Equivalent & Alternatives

The following parts are listed as comparable options for similar telephone line interface applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TEA1062M1	Same die, DIP16 package with SOT38-4/SOT38-9 variant - identical electrical specs and pinout; differs only in mechanical footprint tolerance and mold compound.	No functional difference; used interchangeably in new designs where SOT38-4 mechanical clearance is preferred.	Select TEA1062M1 only when board layout requires alternate DIP16 variant; TEA1062A/C4/M1,112 remains preferred for standard SOT38-1 footprint compliance.
SLIC1200A	Higher integration: includes integrated SLIC, PCM interface, and digital control bus - requires external µC; lacks built-in DTMF decoder and confidence tone.	Targets VoIP gateways and digital telephony systems; not drop-in compatible due to different architecture, pin count (24-pin SOIC), and power domain requirements.	Choose SLIC1200A only for new digital designs requiring PCM output or remote configuration; TEA1062A/C4/M1,112 remains optimal for cost-sensitive analog-only telephone sets.

Compared with TEA1062M1, TEA1062A/C4/M1,112 offers guaranteed SOT38-1 mechanical compliance and full documentation traceability to Philips' original 1997 specification; versus SLIC1200A, it delivers lower system cost, zero firmware dependency, and native DTMF confidence tone - essential for standalone analog telephony.

Availability

TEA1062A/C4/M1,112 is available at Aetrix Electronics and suitable for wired residential telephone sets, office PBX extension units, and DTMF-based security keypads requiring stable component supply and long-term lifecycle support.

Supply support for TEA1062A/C4/M1,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and communication markets. Formerly Philips Semiconductors, it maintains full legacy product support and documentation integrity.

The TEA1062A/C4/M1,112 belongs to NXP's legacy telecom analog interface product line, engineered specifically for cost-effective, robust, and standards-compliant wired telephone equipment - emphasizing low-voltage operation, analog signal fidelity, and minimal external component count.

FAQ

What is the minimum line voltage required for TEA1062A/C4/M1,112 to operate?

The TEA1062A/C4/M1,112 operates down to 1.6 V DC line voltage at 1 mA line current, enabling reliable function in multi-set parallel configurations. Below 9 mA, internal reference voltage drops to sustain operation, though sending/receiving levels are reduced. This behavior is explicitly defined in the Quick Reference Data and Functional Description sections of the official datasheet.

How does the MUTE pin polarity differ between TEA1062A/C4/M1,112 and TEA1062?

The TEA1062A/C4/M1,112 uses active LOW logic on pin 12 (MUTE), whereas the TEA1062 uses active HIGH. This is confirmed in the FEATURES section ("MUTE input: TEA1062A: active LOW") and FUNCTIONAL DESCRIPTION ("When MUTE is LOW or open-circuit, the DTMF input is enabled…"). The difference ensures compatibility with complementary dialler IC families like PCD3310T.

Can TEA1062A/C4/M1,112 drive an electret microphone directly?

Yes - the TEA1062A/C4/M1,112 supports electret microphones via its asymmetrical 32 kΩ input on MIC+ (pin 7), with MIC− (pin 6) tied to VEE. This configuration is explicitly shown in Fig.11(b) and described in the GENERAL DESCRIPTION. No external FET or bias resistor is needed, as the IC provides internal bias current.

What is the purpose of the SLPE pin in TEA1062A/C4/M1,112?

The SLPE pin (pin 16) sets the static DC resistance of the line interface via an external 20 Ω resistor to VEE. As detailed in the FUNCTIONAL DESCRIPTION, it determines the regulated line voltage (VLN), microphone gain, DTMF gain, sidetone level, and maximum output swing. Changing R9 alters all these parameters simultaneously - making SLPE a critical calibration node.

Does TEA1062A/C4/M1,112 include built-in anti-sidetone functionality?

The TEA1062A/C4/M1,112 does not contain an integrated anti-sidetone circuit but is designed to work with external Wheatstone or TEA1060-family bridge networks. As stated in Fig.4 and the Sidetone Suppression section, it provides dedicated nodes (R1, R2, R3, R8, SLPE, Zbal) to implement 32 dB attenuation - meeting ITU-T P.58 requirements when properly configured.

TEA1062A/C4/M1,112 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: -

Package/Case:: 16-DIP (0.300", 7.62mm)

Packaging:: Tube

Product Status:: Active

Function:: Low Voltage Transmission

Interface:: -

Number of Circuits:: 1

Voltage - Supply:: 3.4V

Current - Supply:: 900µA

Power (Watts):: 666 mW

Operating Temperature:: -25°C ~ 75°C

Grade:: -

Qualification:: -

Mounting Type:: Through Hole

Supplier Device Package:: 16-DIP

TEA1062A/C4/M1,112 FAQ

1.How can I place an order for TEA1062A/C4/M1,112 through Aetrix?

Please submit a Request for Quotation (RFQ) for TEA1062A/C4/M1,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TEA1062A/C4/M1,112 reliable?

The price and inventory of TEA1062A/C4/M1,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TEA1062A/C4/M1,112 is usually 5 days.

3.What payment methods are accepted for TEA1062A/C4/M1,112?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TEA1062A/C4/M1,112 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TEA1062A/C4/M1,112?

TEA1062A/C4/M1,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TEA1062A/C4/M1,112 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TEA1062A/C4/M1,112?

For technical support, including TEA1062A/C4/M1,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TEA1062A/C4/M1,112 requirements.

6.How does Aetrix verify that TEA1062A/C4/M1,112 is sourced from the original manufacturer or authorized distributors?

All TEA1062A/C4/M1,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TEA1062A/C4/M1,112 meets industry standards.

7.What is the process for return or replacement of TEA1062A/C4/M1,112?

All TEA1062A/C4/M1,112 units undergo pre-shipment inspection (PSI). If there is an issue with TEA1062A/C4/M1,112, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TEA1062A/C4/M1,112 part is unused and in its original packaging.

Return procedure for TEA1062A/C4/M1,112:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…