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Home > Products > Integrated Circuits (ICs) > Interface > Telecom

NXP Semiconductors TEA1062AT/C4,112

Name: TEA1062AT/C4,112
Brand: NXP Semiconductors
SKU: TEA1062AT/C4,112
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: TEA1062AT/C4,112

Manufacturer:: NXP Semiconductors

Category:: Telecom

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: TEA1062AT/C4,112.pdf

Description:: IC TELECOM INTERFACE 16SO

Quantity:: RFQ Add To RFQ list

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Product details

Overview

TEA1062AT/C4,112 from Philips Semiconductors is a low-voltage telephone line interface IC designed for fully electronic telephone sets. It integrates microphone and earpiece amplifiers, DTMF dialler interface, line voltage regulation (3.55–4.25 V at 15 mA), mute control (active LOW), and automatic line-loss compensation (5.8 dB range). It operates down to 1.6 V DC line voltage and supports dynamic, electret, and piezoelectric transducers in wired telecom systems.

For engineers reviewing the TEA1062AT/C4,112 datasheet, TEA1062AT/C4,112 pinout, TEA1062AT/C4,112 application, or TEA1062AT/C4,112 equivalent, key selection criteria include its SO16 package, active-LOW MUTE logic, 64 kΩ symmetrical microphone input impedance, 31 dB receiving amplifier gain, and compatibility with 36–60 V exchange supply voltages in analog telephony hardware design.

Technical Context

The TEA1062AT/C4,112 implements a dual-stage analog signal path: a high-impedance microphone amplifier (44–52 dB gain adjustable via external R7) feeds the line terminal (LN), while a separate receiving amplifier (20–31 dB gain via R4) drives the earpiece output (QR). Its internal current stabilizer and voltage regulator (VLN = 3.7 V reference + I_SLPE × R9) enable stable operation across varying line currents (1–140 mA).

Line loss compensation is achieved via the AGC pin, where an external resistor (R6) sets a 5.8 dB gain-control range tied to line current-enabling consistent audio performance over 5 km of 0.5 mm copper cable. The IC's anti-sidetone network attenuates transmitted signals by 32 dB before reaching the receiving amplifier, using external passive components (R1–R9, Z_bal) for bridge balancing.

Key Specifications

Parameter	Value and Actual Design Meaning
Line Voltage (VLN)	3.55–4.25 V at 15 mA line current; enables reliable operation on standard POTS lines with headroom for voltage drop.
Microphone Input Impedance	64 kΩ differential (32 kΩ single-ended); supports dynamic, magnetic, piezoelectric, and electret microphones without biasing circuitry.
Receiving Amplifier Gain	29.5–32.5 dB (typ. 31 dB) into 300 Ω; delivers sufficient drive for standard 300 Ω earpieces with low THD.
DTMF Input Gain	24.0–27.0 dB (typ. 25.5 dB); provides confidence tone feedback and robust tone transmission onto the line.
Automatic Gain Control Range	5.8 dB variation vs. line current; compensates for up to 5 km line length (1.2 dB/km attenuation) without manual recalibration.
Mute Logic Polarity	Active LOW on pin 12; disables microphone/receiving paths and enables DTMF input during dialling-critical for correct timing in pulse/DTMF hybrid systems.
Operating Temperature	−25 °C to +75 °C ambient; validated for deployment in residential and small-office telephone hardware environments.

Pinout & Package

TEA1062AT/C4,112 is supplied in a plastic small outline package (SO16) with 16 leads, body width 3.9 mm (SOT109-1), suitable for surface-mount assembly in space-constrained telephone handsets and base stations.

Pin/Terminal	Circuit Role	Design Meaning
LN (1)	Positive line terminal	Main bidirectional speech and signalling path to telephone line; carries amplified microphone output and receives incoming audio.
GAS1/GAS2 (2,3)	Transmit gain adjustment	External resistor (R7) between pins sets microphone amplifier gain from 44 dB to 52 dB-calibrates sensitivity for transducer type.
QR (4)	Non-inverting earpiece output	Drives dynamic/magnetic/piezoelectric earpieces; output impedance 4 Ω ensures low-loss coupling to 300 Ω loads.
GAR (5)	Receive gain adjustment	Resistor (R4) between GAR and QR sets receiving amplifier gain (20–31 dB) to match earpiece sensitivity and sidetone requirements.
MIC−/MIC+ (6,7)	Differential microphone inputs	64 kΩ balanced input accepts dynamic, electret (with FET), or piezoelectric mics; common-mode rejection >82 dB suppresses line noise.
STAB (8)	Current stabilizer reference	Connects to 3.6 kΩ resistor to VEE; sets internal current reference point for line current regulation and stability.
VEE (9)	Negative line terminal	Return path for line current and all internal supplies; serves as analog ground reference for all amplifier stages.
IR (10)	Receiving amplifier input	21 kΩ input impedance accepts line-received audio; feeds non-inverting amplifier stage driving QR output.
DTMF (11)	Dual-tone multi-frequency input	20.7 kΩ input accepts DTMF tones from dialler IC; enabled when MUTE is LOW, providing confidence tone via earpiece.
MUTE (12)	Mute control input	Active LOW logic (TEA1062A variant); disables mic/earpiece paths and enables DTMF during dialling-prevents speech leakage.
VCC (13)	Peripheral supply decoupling	Provides regulated 2.2–3.4 V for external circuits (e.g., dialler ICs); current availability depends on MUTE state and line conditions.
REG (14)	Voltage regulator decoupling	Decoupling node for internal regulator; capacitor to VEE stabilizes reference voltage and reduces ripple on VLN.
AGC (15)	Automatic gain control input	External R6 to VEE configures line-loss compensation curve; enables adaptive gain scaling over 6–70 mA line current range.
SLPE (16)	Slope (DC resistance) adjustment	External R9 to VEE sets static line resistance (20 Ω typical); determines VLN regulation point and influences transmit/receive gain.

Key Features

Feature	Design Value
Low-voltage line operation	Functions down to 1.6 V DC line voltage-enables up to 5 parallel telephone sets on a single line without dropout.
Adjustable static line resistance	R9 (20 Ω typical) between SLPE and VEE sets VLN regulation point and directly impacts microphone gain, DTMF gain, and sidetone level.
Asymmetrical electret input support	32 kΩ single-ended MIC+ input accommodates electret microphones with built-in FET source followers-eliminates need for external bias resistors.
Confidence tone generation	DTMF signal routed to earpiece at reduced level (−17 dB) during dialling-confirms tone transmission without disrupting user experience.
Temperature-compensated reference	Internally generated 3.7 V reference (±0.3 mV/K drift) ensures stable VLN regulation and gain accuracy across −25 °C to +75 °C.
Click-free mute switching	MUTE transitions cause negligible audible clicking on line or earpiece-meets ITU-T P.56 subjective quality requirements for telephony interfaces.

Applications

Wired Telephone Handset	DTMF Dialler Interface
Use Scenario: Full-duplex voice communication in analog corded telephones connected to PSTN lines. IC Role / Device Role / Timing Role: Performs all line interface functions-microphone preamplification, earpiece drive, sidetone suppression, line voltage regulation, and DTMF routing. Use Value: Eliminates discrete transistor-based interface designs; reduces BOM count by integrating regulators, amplifiers, and protection logic in one SO16 IC.	Use Scenario: Integration with CMOS dialler ICs (e.g., PCD3310T) for push-button tone dialling in residential phones. IC Role / Device Role / Timing Role: Provides DTMF input path, confidence tone feedback, and mute-controlled signal gating synchronized to dialler output pulses. Use Value: Enables zero-latency DTMF transmission with audible confirmation-verified in Fig.20 application schematic with PCD3310T.
Multi-Set Parallel Line Support	Electret Microphone Interface
Use Scenario: Deployment of multiple telephones on a single shared line in offices or hotels. IC Role / Device Role / Timing Role: Maintains functional speech amplification and line regulation even at 1 mA line current (VLN = 1.6 V), enabling up to five sets in parallel. Use Value: Extends usable line voltage range beyond legacy ICs-avoids call failure or mute-on-hangup issues in high-impedance line configurations.	Use Scenario: Direct connection of low-cost electret condenser microphones in cost-sensitive telephone designs. IC Role / Device Role / Timing Role: Supplies 32 kΩ single-ended input impedance and internal bias path-no external FET or resistor network required. Use Value: Reduces component count and PCB area versus discrete electret interface solutions; maintains 82 dB CMRR for noise immunity.

Wired Telephone Handset

DTMF Dialler Interface

Use Scenario: Full-duplex voice communication in analog corded telephones connected to PSTN lines.

IC Role / Device Role / Timing Role: Performs all line interface functions-microphone preamplification, earpiece drive, sidetone suppression, line voltage regulation, and DTMF routing.

Use Value: Eliminates discrete transistor-based interface designs; reduces BOM count by integrating regulators, amplifiers, and protection logic in one SO16 IC.

Use Scenario: Integration with CMOS dialler ICs (e.g., PCD3310T) for push-button tone dialling in residential phones.

IC Role / Device Role / Timing Role: Provides DTMF input path, confidence tone feedback, and mute-controlled signal gating synchronized to dialler output pulses.

Use Value: Enables zero-latency DTMF transmission with audible confirmation-verified in Fig.20 application schematic with PCD3310T.

Multi-Set Parallel Line Support

Electret Microphone Interface

Use Scenario: Deployment of multiple telephones on a single shared line in offices or hotels.

IC Role / Device Role / Timing Role: Maintains functional speech amplification and line regulation even at 1 mA line current (VLN = 1.6 V), enabling up to five sets in parallel.

Use Value: Extends usable line voltage range beyond legacy ICs-avoids call failure or mute-on-hangup issues in high-impedance line configurations.

Use Scenario: Direct connection of low-cost electret condenser microphones in cost-sensitive telephone designs.

IC Role / Device Role / Timing Role: Supplies 32 kΩ single-ended input impedance and internal bias path-no external FET or resistor network required.

Use Value: Reduces component count and PCB area versus discrete electret interface solutions; maintains 82 dB CMRR for noise immunity.

Equivalent & Alternatives

The following parts are listed as comparable options for similar telephone line interface applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TEA1062A	DIP16 package (SOT38-1); identical electrical specs and pinout but through-hole mounting.	Preferred for prototyping, repair, or legacy through-hole PCBs where reflow-compatible SO16 is not feasible.	Select TEA1062AT/C4,112 for automated SMT production; choose TEA1062A only if board layout mandates DIP16 footprint.
SLIC1062A	Functionally equivalent line interface IC with same gain ranges, AGC, and mute logic-but manufactured by STMicroelectronics with minor thermal derating (R_{th j-a} = 115 K/W vs. 110 K/W).	Valid drop-in replacement in new designs where Philips sourcing is constrained; requires validation of SLPE/REG decoupling values per ST datasheet.	Use SLIC1062A only after verifying R9, R6, and C3 values match Philips-recommended 20 Ω, 110 kΩ, and 4.7 µF respectively.

Compared with TEA1062A, TEA1062AT/C4,112 offers identical analog performance in a smaller SO16 package for higher-density layouts, while SLIC1062A provides second-source availability with near-identical functionality but requires thermal margin verification under full-load conditions.

Availability

TEA1062AT/C4,112 is available at Aetrix Electronics and suitable for wired telephone handsets, DTMF dialler integration, and multi-set parallel line deployments requiring stable component supply across industrial telecom hardware lifecycles.

Supply support for TEA1062AT/C4,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Philips Semiconductors (now NXP Semiconductors) is a pioneer in analog telecom ICs, delivering high-reliability mixed-signal solutions for wired communications infrastructure since the 1970s.

The TEA1062 family was engineered specifically for cost-effective, low-power analog telephone sets-integrating line interface, amplification, regulation, and dialling support in a single IC to replace discrete transistor-based designs.

FAQ

What is the minimum line voltage required for TEA1062AT/C4,112 to operate?

The TEA1062AT/C4,112 operates down to 1.6 V DC line voltage at 1 mA line current, as confirmed in the Quick Reference Data table (VLN = 1.6 V typ. at I_line = 1 mA). This low-voltage capability enables up to five telephone sets to operate in parallel on a single line without dropout. Performance-including microphone and receiving amplifier levels-is reduced below 3.55 V, but core dialling and basic audio functions remain functional.

How does the MUTE pin function on TEA1062AT/C4,112?

The MUTE pin (pin 12) on TEA1062AT/C4,112 is active LOW, meaning microphone and receiving amplifier paths are disabled-and DTMF input is enabled-when the pin is pulled to VEE (0 V). This logic matches the TEA1062A variant designation. MUTE transitions cause negligible audible clicking on the line or earpiece output, satisfying telephony quality standards. When line current falls below 6 mA, the DTMF amplifier remains active regardless of MUTE state.

Can TEA1062AT/C4,112 support electret microphones directly?

Yes, TEA1062AT/C4,112 supports electret microphones directly via its asymmetrical 32 kΩ single-ended MIC+ input (pin 7), which provides the necessary bias path for built-in FET source followers. No external bias resistor or JFET is required. This is explicitly stated in the FEATURES section and verified in Fig.11(b) of the datasheet, confirming compatibility with standard electret capsules used in consumer telephones.

What external components define the line-loss compensation behavior of TEA1062AT/C4,112?

The line-loss compensation behavior of TEA1062AT/C4,112 is defined by resistor R6 connected between AGC (pin 15) and VEE. Its value (e.g., 110 kΩ for 48 V exchange supply with 600 Ω feeding bridge) sets the 5.8 dB gain-control range across 6–70 mA line current, as shown in Fig.13 and Table 1. R6 selection must match the specific exchange supply voltage (V_exch) and feeding bridge resistance (R_exch) per the datasheet's lookup table.

Is TEA1062AT/C4,112 pin-compatible with TEA1062T?

Yes, TEA1062AT/C4,112 is pin-compatible with TEA1062T-the "A" suffix denotes the active-LOW MUTE version, and both share the SO16 (SOT109-1) package, identical pinout, and full electrical compatibility. The /C4,112 suffix indicates Philips' tape-and-reel packaging variant; no functional difference exists between TEA1062AT/C4,112 and TEA1062T beyond packaging and reel orientation.

TEA1062AT/C4,112 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: -

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tube

Product Status:: Obsolete

Function:: Low Voltage Transmission

Interface:: -

Number of Circuits:: 1

Voltage - Supply:: 3.4V

Current - Supply:: 900µA

Power (Watts):: 454 mW

Operating Temperature:: -25°C ~ 75°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SO

TEA1062AT/C4,112 FAQ

1.How can I place an order for TEA1062AT/C4,112 through Aetrix?

Please submit a Request for Quotation (RFQ) for TEA1062AT/C4,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TEA1062AT/C4,112 reliable?

The price and inventory of TEA1062AT/C4,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TEA1062AT/C4,112 is usually 5 days.

3.What payment methods are accepted for TEA1062AT/C4,112?

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4.How is shipping managed for TEA1062AT/C4,112?

TEA1062AT/C4,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TEA1062AT/C4,112 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TEA1062AT/C4,112?

For technical support, including TEA1062AT/C4,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TEA1062AT/C4,112 requirements.

6.How does Aetrix verify that TEA1062AT/C4,112 is sourced from the original manufacturer or authorized distributors?

All TEA1062AT/C4,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TEA1062AT/C4,112 meets industry standards.

7.What is the process for return or replacement of TEA1062AT/C4,112?

All TEA1062AT/C4,112 units undergo pre-shipment inspection (PSI). If there is an issue with TEA1062AT/C4,112, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TEA1062AT/C4,112 part is unused and in its original packaging.

Return procedure for TEA1062AT/C4,112:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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