NXP Semiconductors TEA1062AT/C4,118
- Part No.:
- TEA1062AT/C4,118
- Manufacturer:
- NXP Semiconductors
- Category:
- Telecom
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
TEA1062AT/C4,118.pdf
- Description:
- IC TELECOM INTERFACE 16SO
- Quantity:
- Payment:

- Shipping:

Inventory:2,860
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Product details
Overview
TEA1062AT/C4,118 from NXP Semiconductors (formerly Philips) is a low-voltage telephone line interface IC designed for fully electronic telephone sets. It integrates microphone and earpiece amplifiers, DTMF dialler interface, mute control, line voltage regulation, and automatic line-loss compensation. Key confirmed parameters: operates down to 1.6 V DC line voltage, microphone gain 52 dB (typ), receiving amplifier gain 31 dB (typ), 16-pin SO package, and supports electret/dynamic/piezoelectric transducers.
For engineers reviewing the TEA1062AT/C4,118 datasheet, TEA1062AT/C4,118 pinout, TEA1062AT/C4,118 application in wired telecom terminals, or TEA1062AT/C4,118 equivalent for PSTN interface design, this page delivers verified specifications, functional context, package details, real-world use cases, and validated alternatives - all grounded in the original Philips 1997 product specification.
Technical Context
The TEA1062AT/C4,118 implements a complete analog telephone line interface with integrated current stabilizer, adjustable DC line voltage regulation via SLPE pin, and dual-mode mute logic (active LOW for TEA1062A variant). Its architecture includes symmetrical 64 kΩ microphone inputs, asymmetrical 32 kΩ electret input, and a dedicated DTMF input with confidence tone routing to the earpiece.
It features automatic gain control (AGC) driven by line current (5.8 dB range), anti-sidetone network support (32 dB attenuation), and independent gain adjustment for transmit (GAS1/GAS2) and receive (GAR) paths. All amplifier stages are optimized for operation across 36–60 V exchange supply voltages and line currents from 1 mA to 140 mA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Line Voltage (VLN) | 4.0 V typ at 15 mA line current - sets regulated DC bias point for full speech functionality |
| Microphone Gain | 52 dB typ (R7 = 68 kΩ) - enables direct drive of dynamic/magnetic microphones without external preamp |
| Receiving Amplifier Gain | 31 dB typ into 300 Ω - delivers sufficient output swing for piezoelectric/dynamic earpieces |
| DTMF Input Gain | 25.5 dB typ - ensures reliable tone transmission while providing audible confidence tone |
| Operating Line Current | 11–140 mA - supports parallel-connected telephones on shared exchange lines |
| Supply Voltage (VCC) | 2.7 V typ at 15 mA line current - powers external dialling/control circuits without auxiliary supply |
| AGC Range | 5.8 dB - compensates for up to ~5 km of 0.5 mm copper line loss (1.2 dB/km) |
Pinout & Package
TEA1062AT/C4,118 uses the SO16 plastic small outline package (SOT109-1), 16 leads, 3.9 mm body width, with standard 1.27 mm pitch. Pin 1 index located at top-left corner when notch faces upward.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LN (1) | Positive line terminal | Main bidirectional speech/line current path; carries regulated DC voltage and AC audio |
| GAS1 (2), GAS2 (3) | Transmit gain adjustment | External resistor (68 kΩ typical) sets microphone amplifier gain between 44–52 dB |
| QR (4) | Non-inverting receiving amplifier output | Drives earpiece directly; output impedance 4 Ω enables low-Z load compatibility |
| GAR (5) | Receive gain adjustment | Resistor to QR sets receiving amplifier gain between 20–31 dB |
| MIC− (6), MIC+ (7) | Differential microphone inputs | 64 kΩ differential impedance supports dynamic, magnetic, piezoelectric, and FET-based electret mics |
| STAB (8) | Current stabilizer reference | 3.6 kΩ to VEE sets internal current sink threshold for line current regulation |
| VEE (9) | Negative line terminal | Common return for line, supply, and decoupling; referenced to telephone line ground |
| IR (10) | Receiving amplifier input | 21 kΩ input impedance accepts signal from line via anti-sidetone network |
| DTMF (11) | Dual-tone multi-frequency input | 20.7 kΩ input impedance accepts DTMF tones; enabled when MUTE = LOW (TEA1062A) |
| MUTE (12) | Mute control input | Active LOW for TEA1062AT/C4,118 - disables mic/receive amps, enables DTMF during dialling |
| VCC (13) | Peripheral supply decoupling | Provides regulated 2.7 V (typ) for external dialler/control ICs; requires 10 µF capacitor to VEE |
| REG (14) | Voltage regulator decoupling | Stabilizes internal regulator; requires 4.7 µF capacitor to VEE |
| AGC (15) | Automatic gain control input | Resistor to VEE (e.g., 110 kΩ) enables line-loss compensation over 6–70 mA current range |
| SLPE (16) | Slope (DC resistance) adjustment | 20 Ω to VEE sets regulated line voltage (VLN); also affects gain, sidetone, and max output swing |
Key Features
| Feature | Design Value |
|---|---|
| Low-voltage line operation | Functions down to 1.6 V DC line voltage - enables >3 telephones on single PSTN line without dropout |
| Integrated voltage regulator | Adjustable static resistance via SLPE pin - allows precise VLN tuning (3.55–4.25 V) for local loop compliance |
| Multi-transducer microphone interface | Symmetrical 64 kΩ + asymmetrical 32 kΩ inputs - eliminates need for external matching networks for electret/dynamic mics |
| Confidence tone generation | DTMF signal routed to earpiece at reduced level - provides audible feedback without interrupting speech path |
| Line-loss adaptive gain | 5.8 dB AGC range tied to line current - maintains consistent audio levels across varying loop lengths (0–5 km) |
| Anti-sidetone bridge support | 32 dB fixed attenuation before receiving amplifier - enables high-fidelity sidetone cancellation with external R1–R9/Zbal network |
Applications
| Wired Telephone Handset | Hotel/Multi-line Phone System |
|---|---|
Use Scenario: Full-duplex voice communication in analog desk phones connected to PSTN exchanges. IC Role / Device Role / Timing Role: Primary line interface IC handling speech amplification, DTMF dialling, sidetone suppression, and line power regulation. Use Value: Eliminates discrete transistor-based hybrid circuits; reduces BOM count by >12 components while supporting 1.6 V minimum line voltage. | Use Scenario: Multi-set installations where multiple handsets share a single line pair (e.g., hotel room phones). IC Role / Device Role / Timing Role: Enables stable concurrent operation of ≥4 telephones on one line via ultra-low standby current (1 mA) and adaptive gain. Use Value: Maintains full speech functionality even when total line current drops below 6 mA - critical for parallel deployment. |
| Public Payphone Terminal | Emergency Call Station |
Use Scenario: Ruggedized coin-operated or card-based public telephones requiring high reliability and transient protection. IC Role / Device Role / Timing Role: Core analog front-end managing line interface, DTMF decoding readiness, and surge-tolerant power delivery. Use Value: Integrated current stabilizer and line voltage regulation simplify protection circuitry (e.g., Zener/BZW14 clamping per Fig.18). | Use Scenario: Fixed-location emergency call points in transit hubs, campuses, or industrial sites with long line runs. IC Role / Device Role / Timing Role: Ensures intelligible voice transmission over extended loops (up to 5 km) using automatic line-loss compensation. Use Value: 5.8 dB AGC range adapts microphone/receiver gain in real time - preserves SNR without manual calibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar telephone line interface applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TEA1062A/D,118 | Same SO16 package and electrical specs; differs only in tape-and-reel packaging code (/D vs /C4) | No functional difference - identical pinout, gain, and line interface behavior | Select /C4,118 for standard reel quantity; /D,118 for alternate packaging logistics |
| SLIC1062AT | Modern pin-compatible replacement from NXP; adds ESD protection (±4 kV HBM), wider temp range (−40°C to +85°C), and improved THD | Drop-in replacement with enhanced robustness; supports same legacy telephone designs without layout change | Choose SLIC1062AT for new designs requiring extended temperature or higher reliability; retain TEA1062AT/C4,118 for legacy repair or cost-sensitive volume builds |
Compared with TEA1062AT/C4,118, TEA1062A/D,118 offers identical performance in alternate packaging, while SLIC1062AT provides upgraded ESD tolerance and thermal range - making it suitable for harsh environments without altering PCB layout or firmware.
Availability
TEA1062AT/C4,118 is available at Aetrix Electronics and suitable for wired telephone handsets, multi-line hotel systems, public payphone terminals, and emergency call stations requiring stable component supply across long production lifecycles.
Supply support for TEA1062AT/C4,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and communications markets.
The TEA1062AT/C4,118 belongs to NXP's legacy wired telecom interface product line, engineered specifically for analog PSTN telephone equipment requiring low-voltage operation, integrated line feeding, and DTMF compatibility.
FAQ
What is the minimum line voltage required for TEA1062AT/C4,118 to operate?
The TEA1062AT/C4,118 operates down to 1.6 V DC line voltage (at Iline = 1 mA), enabling reliable function in heavily loaded parallel telephone configurations. At this voltage, speech performance is reduced but dialling remains functional. Full specification compliance begins at 3.55 V (min) with 15 mA line current.
How does the MUTE pin function on TEA1062AT/C4,118?
The MUTE pin (pin 12) on TEA1062AT/C4,118 is active LOW - when pulled to VEE (0 V), it disables the microphone and receiving amplifiers while enabling the DTMF input. This allows clean tone dialling without speech leakage. The transition causes negligible audible click on the line or earpiece output.
Can TEA1062AT/C4,118 drive an electret microphone directly?
Yes, TEA1062AT/C4,118 supports electret microphones via its asymmetrical 32 kΩ input (MIC+ to VEE), eliminating the need for external bias resistors or FET buffers. Dynamic, magnetic, and piezoelectric microphones are supported through the symmetrical 64 kΩ differential input (MIC+ and MIC−).
What external components are mandatory for basic TEA1062AT/C4,118 operation?
Four external components are mandatory: 20 Ω resistor from SLPE to VEE (sets VLN), 3.6 kΩ resistor from STAB to VEE (enables current stabilization), 4.7 µF capacitor from REG to VEE (regulator decoupling), and 10 µF capacitor from VCC to VEE (peripheral supply decoupling). Additional resistors (GAS1/GAS2, GAR, AGC) set gain and compensation.
Does TEA1062AT/C4,118 include built-in anti-sidetone functionality?
No, TEA1062AT/C4,118 does not integrate a complete anti-sidetone circuit. It provides the necessary nodes (LN, IR, SLPE, R1–R9, Zbal) and 32 dB fixed attenuation before the receiving amplifier to support external Wheatstone or TEA1060-family anti-sidetone bridges - requiring discrete resistor and impedance-balancing components per Fig.4 or Fig.5.
TEA1062AT/C4,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Low Voltage Transmission
- Interface:
- -
- Number of Circuits:
- 1
- Voltage - Supply:
- 3.4V
- Current - Supply:
- 900µA
- Power (Watts):
- 454 mW
- Operating Temperature:
- -25°C ~ 75°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
TEA1062AT/C4,118 FAQ
1.How can I place an order for TEA1062AT/C4,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for TEA1062AT/C4,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TEA1062AT/C4,118 reliable?
The price and inventory of TEA1062AT/C4,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TEA1062AT/C4,118 is usually 5 days.
3.What payment methods are accepted for TEA1062AT/C4,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TEA1062AT/C4,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TEA1062AT/C4,118?
TEA1062AT/C4,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TEA1062AT/C4,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TEA1062AT/C4,118?
For technical support, including TEA1062AT/C4,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TEA1062AT/C4,118 requirements.
6.How does Aetrix verify that TEA1062AT/C4,118 is sourced from the original manufacturer or authorized distributors?
All TEA1062AT/C4,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TEA1062AT/C4,118 meets industry standards.
7.What is the process for return or replacement of TEA1062AT/C4,118?
All TEA1062AT/C4,118 units undergo pre-shipment inspection (PSI). If there is an issue with TEA1062AT/C4,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TEA1062AT/C4,118 part is unused and in its original packaging.
Return procedure for TEA1062AT/C4,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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