My Inquiry
My Account
NXP Semiconductors TEA18363T/1J
- Part No.:
- TEA18363T/1J
- Manufacturer:
- NXP Semiconductors
- Category:
- AC DC Converters, Offline Switches
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
TEA18363T/1J.pdf
- Description:
- IC OFFLINE SWITCH FLYBACK 8SO
- Quantity:
- Payment:
- Shipping:
Inventory:9,119
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TEA18363T/1J from NXP Semiconductors is a GreenChip SMPS controller IC designed for quasi-resonant flyback converters up to 75 W. It integrates high-voltage start-up, valley-switching control, frequency reduction, burst-mode operation, and mains-independent OverPower Protection (OPP). Its SOI process enables low standby current (235 µA in burst non-switching), audible-noise-free operation (25 kHz min switching, <800 Hz burst), and integrated X-capacitor discharge - used in compact AC/DC adapters and open-frame power supplies.
For engineers reviewing the TEA18363T/1J datasheet, TEA18363T/1J pinout, TEA18363T/1J application, or TEA18363T/1J equivalent, key selection criteria include its 8-pin SO8 package, 14.9 V typical Vstartup, 300 mA/750 mA driver sourcing/sinking capability, 55 µs max on-time limit, and support for green-mode efficiency down to <30 mW no-load input power.
Technical Context
The TEA18363T/1J implements a multi-mode control architecture: quasi-resonant (QR) at high load, frequency-reduced DCM at medium load, and digitally controlled burst mode below 25 kHz switching - all with valley detection via the AUX pin. Its HV pin performs mains voltage sensing, brown-in/out detection, and active X-cap discharge using pulsed current sampling.
Protection logic includes cycle-by-cycle overcurrent via ISENSE, latched OTP and OVP (4-pulse counter), time-limited OPP (40 ms startup / 200 ms normal), and safe-restart (800 ms) or latch modes depending on fault type. VCC regulation during start-up and protection is maintained via the HV current source, enabling minimal external capacitance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Vstartup | 14.9 V typical - defines minimum VCC required to activate internal circuitry; enables reliable start-up from HV pin under wide-input conditions. |
| Istartup(HV) | 1.1 mA typical - high-voltage start-up current sourced from mains via HV pin; supports direct high-voltage charging of VCC capacitor. |
| Driver Output | 300 mA sink / 750 mA source - drives external MOSFET gate directly or via small resistor; ensures fast turn-on/turn-off for QR valley switching. |
| Burst Mode Current | 235 µA typical (non-switching phase) - minimizes IC supply current during idle periods, enabling <30 mW no-load input power. |
| Max On-Time | 55 µs - hardware-limited gate drive duration prevents transformer saturation and MOSFET overstress under overload. |
| OVP Detection | 4-pulse counter on AUX pin - rejects ESD/lightning-induced false triggers while ensuring accurate output overvoltage shutdown. |
| OPP Time-out | 200 ms (normal), 40 ms (start-up) - allows temporary 150 % overpower during transient loads, then limits output to <5 W under short-circuit. |
Pinout & Package
TEA18363T/1J is housed in an 8-lead plastic small outline package (SO8, SOT96-1), 3.9 mm body width, with standard JEDEC footprint and thermal resistance Rth(j-a) = 91 K/W (free air).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (Pin 1) | Supply voltage input | Regulated internal supply rail; charged via HV pin at start-up, then sustained by auxiliary winding; clamped to Vstartup during protection. |
| GND (Pin 2) | Ground reference | Common return for all analog and digital circuitry; serves as reference for ISENSE, CTRL, and AUX measurements. |
| DRIVER (Pin 3) | Gate driver output | Push-pull output driving external MOSFET gate; 300 mA source / 750 mA sink; limited to 10.5 V max output voltage. |
| ISENSE (Pin 4) | Primary current sense input | Monitors MOSFET drain current via sense resistor; triggers overcurrent protection and controls soft-start timing via external capacitor. |
| AUX (Pin 5) | Auxiliary winding interface | Measures demagnetization timing, valley point, input voltage (for OPP), and output voltage (for OVP); enables single-pin multi-function sensing. |
| CTRL (Pin 6) | Optocoupler feedback input | Regulates output voltage via opto-transistor current; enters burst mode when voltage drops below 0.5 V; clamped during burst period. |
| n.c. (Pin 7) | No connection | Internally unconnected; must remain floating; no external component or trace required. |
| HV (Pin 8) | High-voltage start-up & discharge | Sources start-up current from rectified mains; samples mains voltage for brown-in/out detection; actively discharges X-capacitor when mains removed. |
Key Features
| Feature | Design Value |
|---|---|
| Valley-switching across all modes | Minimizes MOSFET switching losses by triggering gate drive at transformer drain-voltage valleys - effective in QR, DCM, and FR modes. |
| Integrated X-capacitor discharge | Patented NXP circuit on HV pin automatically discharges line-to-line X-capacitors within seconds after AC removal - meets IEC 62368-1 safety requirements. |
| Adjustable soft start | Externally set via ISENSE pin capacitor/resistor; prevents inrush current and audible noise during power-up or restart. |
| Sub-800 Hz burst repetition rate | Digital burst control ensures burst frequency remains below audible range while maintaining ≥25 kHz switching frequency - eliminates coil whine. |
| Mains-independent OPP | Compensates for input voltage variation using AUX pin measurement; delivers stable 150 % overpower allowance regardless of 85–265 VAC input. |
Applications
| AC/DC Adapters | Open-Frame Power Supplies |
|---|---|
Use Scenario: Wall-mounted USB chargers and laptop adapters requiring <30 mW no-load power and CE/ERP Tier 2 compliance. IC Role / Device Role / Timing Role: Primary-side controller managing QR flyback topology, real-time valley detection, and burst-mode sequencing. Use Value: Eliminates opto-coupler bias winding and secondary-side TL431, reducing BOM count by ≥3 components while achieving <0.1 W no-load consumption. |
Use Scenario: Industrial control power modules needing robust brown-out recovery and 75 W continuous output with <50 °C ambient derating. IC Role / Device Role / Timing Role: System-level SMPS supervisor coordinating HV start-up, mains monitoring, and latched OTP/OVP shutdown. Use Value: Enables single-stage flyback design with integrated X-cap discharge and 800 ms safe-restart - avoids external bleeder networks and discrete protection ICs. |
| Smart Home Power Modules | LED Driver Power Stages |
Use Scenario: Low-power IoT hubs and voice assistant devices requiring ultra-low standby power and EMI-compliant burst operation. IC Role / Device Role / Timing Role: Efficiency-optimized controller executing sub-800 Hz burst cycles with 3-pulse minimum and dynamic pulse count adjustment. Use Value: Achieves ERP Lot 6 compliance with <0.3 W input at no-load and passes EN 55022 Class B conducted EMI without Y-cap or common-mode choke. |
Use Scenario: Constant-voltage LED drivers for architectural lighting where output regulation stability and short-circuit foldback are critical. IC Role / Device Role / Timing Role: Precision feedback controller using CTRL pin current modulation and AUX-based OVP with 4-pulse hysteresis. Use Value: Provides accurate ±5 % output regulation over 10:1 load range and immediate latched shutdown on LED string open/short - eliminating external OVP comparators. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SMPS controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28740DR | TI device uses primary-side sensing only; lacks integrated HV start-up and X-cap discharge; requires external HV resistor network. | Targeted at cost-sensitive consumer adapters where X-cap discharge is handled externally; lower integration increases layout complexity. | Select UCC28740DR only if existing design already includes HV resistive start-up and discrete X-cap bleed circuitry. |
| ICE2QS03G | Infineon quasi-resonant controller offers higher peak current (1 A vs 750 mA sink), but no burst-mode optimization below 25 kHz; higher ICC(oper) = 1.2 mA. | Better suited for higher-power (>100 W) flyback designs with less stringent no-load requirements; not optimized for sub-30 mW standby. | Choose ICE2QS03G when designing >90 W supplies with legacy transformer sets and no ERP Tier 2 constraints. |
Compared with UCC28740DR and ICE2QS03G, the TEA18363T/1J uniquely combines integrated HV start-up, patented X-cap discharge, and audibly silent burst mode - making it the only option among the three that satisfies both IEC 62368-1 safety and ERP Lot 6 efficiency mandates in a single SO8 package.
Availability
TEA18363T/1J is available at Aetrix Electronics and suitable for AC/DC adapters, open-frame power supplies, smart home modules, and LED driver power stages requiring stable component supply, long-term lifecycle support, and full traceability.
Supply support for TEA18363T/1J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with core expertise in power management and energy-efficient IC design.
The TEA18363T/1J belongs to NXP's GreenChip SMPS controller family, engineered specifically for high-efficiency, low-BOM-count flyback converters targeting global energy regulations including ERP, ENERGY STAR, and DoE Level VI.
FAQ
What is the minimum VCC voltage required for TEA18363T/1J to begin operation?
The TEA18363T/1J requires a minimum VCC voltage of 13.4 V (typical 14.9 V, max 16.4 V) to exit undervoltage lockout and initiate soft-start sequencing. Below this threshold, the IC remains in ultra-low-current start-up mode (40 µA), with DRIVER disabled and internal logic held inactive. This Vstartup level ensures reliable activation even under low-line conditions when powered via the HV pin.
How does TEA18363T/1J achieve no-audio-noise burst mode operation?
The TEA18363T/1J achieves no-audio-noise burst mode by enforcing two strict frequency boundaries: a minimum switching frequency of 25 kHz (above human hearing) and a maximum burst repetition rate of 800 Hz (below audible range). Its digital burst controller dynamically adjusts pulse count per burst - never dropping below 3 pulses - while clamping CTRL pin voltage and minimizing non-switching supply current to 235 µA.
Does TEA18363T/1J support direct connection to a 650 V MOSFET gate without external components?
Yes - the TEA18363T/1J DRIVER pin provides 300 mA sourcing and 750 mA sinking capability with 10.5 V output clamping, enabling direct gate drive of standard 650 V superjunction MOSFETs (e.g., STP12NM60FD, FDPF12N50) without external buffers or level shifters. A small series gate resistor (typically 10 Ω) is still recommended for EMI control and ringing suppression.
What protection features are latched versus auto-restarting in TEA18363T/1J?
In the TEA18363T/1J, OverTemperature Protection (OTP) and OverVoltage Protection (OVP via AUX) trigger latched shutdown, requiring AC removal to reset. In contrast, OverPower Protection time-out, maximum on-time violation, and brownout events initiate safe-restart mode - automatically resuming operation after 800 ms once mains voltage exceeds brown-in threshold and CTRL pin voltage rises above restart level.
Can TEA18363T/1J be used in discontinuous conduction mode (DCM) flyback designs without valley skipping?
No - the TEA18363T/1J inherently employs valley skipping in DCM operation to prevent high-frequency instability and excessive EMI. Its control logic detects the first valid valley after demagnetization and skips subsequent valleys until the next switching cycle begins. This behavior is fixed in silicon and cannot be disabled; DCM operation always includes valley-skip functionality for consistent efficiency and noise performance.
TEA18363T/1J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- GreenChip™
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Isolation:
- Isolated
- Internal Switch(s):
- No
- Voltage - Breakdown:
- -
- Topology:
- Flyback
- Voltage - Start Up:
- 14.9 V
- Voltage - Supply (Vcc/Vdd):
- 9.9V ~ 30V
- Duty Cycle:
- -
- Frequency - Switching:
- 25kHz ~ 132.5kHz
- Power (Watts):
- 75 W
- Fault Protection:
- Over Power, Over Temperature, Over Voltage
- Control Features:
- -
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 8-SO
- Mounting Type:
- Surface Mount
TEA18363T/1J FAQ
1.How can I place an order for TEA18363T/1J through Aetrix?
Please submit a Request for Quotation (RFQ) for TEA18363T/1J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TEA18363T/1J reliable?
The price and inventory of TEA18363T/1J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TEA18363T/1J is usually 5 days.
3.What payment methods are accepted for TEA18363T/1J?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TEA18363T/1J transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TEA18363T/1J?
TEA18363T/1J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TEA18363T/1J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TEA18363T/1J?
For technical support, including TEA18363T/1J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TEA18363T/1J requirements.
6.How does Aetrix verify that TEA18363T/1J is sourced from the original manufacturer or authorized distributors?
All TEA18363T/1J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TEA18363T/1J meets industry standards.
7.What is the process for return or replacement of TEA18363T/1J?
All TEA18363T/1J units undergo pre-shipment inspection (PSI). If there is an issue with TEA18363T/1J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TEA18363T/1J part is unused and in its original packaging.
Return procedure for TEA18363T/1J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TEA18363T/1J Tags
-
LNK6407D-TL
Power Integrations
-
LNK3204D-TL
Power Integrations
-
SR10LG-G
Microchip Technology
-
TNY285DG-TL
Power Integrations
-
LNK304DN-TL
Power Integrations
-
TNY285KG-TL
Power Integrations
-
LNK3206D-TL
Power Integrations
-
LNK623DG-TL
Power Integrations
-
TNY286PG
Power Integrations
-
LNK624DG-TL
Power Integrations
-
LNK604DG-TL
Power Integrations
-
UCC28704DBVR-1
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
