NXP Semiconductors TEA1892TS/1Z

Overview

TEA1892TS/1Z from NXP Semiconductors is a synchronous rectifier (SR) controller IC for secondary-side operation in discontinuous conduction mode (DCM) and quasi-resonant (QR) flyback converters. It features an 8.5–38 V supply range, 10 V driver output, selectable −42 mV/−30 mV regulation voltage, 1.5 µs minimum active time, and SOI process fabrication - enabling high-efficiency adapter designs with minimal external components.

For engineers reviewing the TEA1892TS/1Z datasheet, TEA1892TS/1Z pinout, TEA1892TS/1Z application, or TEA1892TS/1Z equivalent, this page delivers verified functional role, timing behavior, driver capability, UVLO thresholds, and SR sense-level selection logic required for flyback SR stage validation and layout-critical gate drive design.

Technical Context

The TEA1892TS/1Z implements zero-current detection via SRSENSE pin sensing at −12 mV deactivation threshold, with blanking time of 1.5 µs to suppress ringing-induced false turn-off. Its driver delivers 400 mA source / 2.7 A sink current and regulates output to maintain precise −42 mV or −30 mV on SRSENSE depending on SELREG pin state.

Start-up occurs at VCC ≥ 8.5 V (typical), with 0.5 V hysteresis; UVLO re-engages below 8.0 V. Internal bandgap references and SOI process ensure stable operation across −40 °C to +150 °C junction temperature, supporting no-load-to-full-load efficiency optimization in compact adapters.

Key Specifications

Pinout & Package

TEA1892TS/1Z is housed in a TSOP6 (SOT457) plastic surface-mounted package with 6 leads, optimized for compact secondary-side PCB placement near the SR MOSFET.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous rectifier controller applications.

Compared with NCP4307DR2G, TEA1892TS/1Z offers adjustable regulation and built-in blanking for improved noise immunity; compared with SiHP20N60E, it integrates full timing, regulation, and drive - reducing BOM count by three devices and enabling direct drop-in replacement of diode-based secondary stages.

Availability

TEA1892TS/1Z is available at Aetrix Electronics and suitable for USB-C PD adapters, laptop power supplies, smartphone fast-chargers, and IoT wall plug adapters requiring stable component supply, long-lifecycle support, and qualification-grade traceability.

Supply support for TEA1892TS/1Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer electronics.

The TEA1892TS/1Z belongs to NXP's GreenChip family of high-efficiency power conversion ICs, designed specifically to replace lossy diode rectification in flyback SMPS with integrated, low-component-count synchronous rectification control.

FAQ

What is the function of the SELREG pin on the TEA1892TS/1Z?

The SELREG pin on the TEA1892TS/1Z selects the driver regulation voltage level: grounding it sets V_reg(drv) to −42 mV (typical), while leaving it open selects −30 mV (typical). This adjustment tailors the SR MOSFET conduction window to optimize R_DS(on) utilization versus switching loss, and the internal 10 µA pull-up ensures reliable open-state detection. The TEA1892TS/1Z uses this pin to adapt to different MOSFET gate charge characteristics without external components.

Does the TEA1892TS/1Z support high-side or low-side synchronous rectification configurations?

Yes, the TEA1892TS/1Z supports both high-side and low-side synchronous rectification, as confirmed by Figures 4 and 5 in the official datasheet. In high-side configuration, the SR MOSFET is placed between transformer secondary and output rail; in low-side, it is placed between secondary and ground. The TEA1892TS/1Z senses voltage polarity and magnitude on the SRSENSE pin regardless of topology, and its DRIVER output adapts accordingly - making the TEA1892TS/1Z suitable for either implementation without hardware change.

What is the purpose of the 1.5 µs blanking time in the TEA1892TS/1Z?

The 1.5 µs blanking time in the TEA1892TS/1Z disables SRSENSE sensing immediately after driver turn-on to prevent false turn-off caused by high-frequency ringing at the start of the secondary stroke. This timing is fixed and internally generated, ensuring robust operation across varying transformer parasitics and PCB layouts. Without this blanking, ringing could falsely trigger deactivation, increasing conduction loss - a critical safeguard explicitly implemented in the TEA1892TS/1Z for reliable DCM/QR flyback operation.

How does the TEA1892TS/1Z achieve zero-current switching (ZCS)?

The TEA1892TS/1Z achieves zero-current switching by monitoring the SRSENSE pin voltage and deactivating the DRIVER output when it rises to −12 mV (typical), which corresponds to near-zero secondary current. This precise threshold detection eliminates residual conduction loss during MOSFET turn-off and removes the need for a separate standby mode. The TEA1892TS/1Z performs this detection autonomously using internal comparators and timing logic - a core feature enabling ultra-low no-load power in adapters using the TEA1892TS/1Z.

What is the maximum switching frequency supported by the TEA1892TS/1Z?

The TEA1892TS/1Z supports a maximum switching frequency of 250 kHz, as specified in Table 5 of the NXP datasheet under "fsw(max)". This limit ensures sufficient time for internal timing functions - including blanking, regulation, and deactivation - to execute reliably within each switching cycle. Operation beyond 250 kHz may compromise SR timing accuracy and zero-current detection integrity, so the TEA1892TS/1Z is optimized for standard DCM and QR flyback converters operating up to this frequency ceiling.