NXP Semiconductors TEA19032CABT/1J
- Part No.:
- TEA19032CABT/1J
- Manufacturer:
- NXP Semiconductors
- Category:
- Controllers
- Package:
- 10-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
TEA19032CABT/1J.pdf
- Description:
- SMARTCHARG PROTO CONTR USBPD3+PP
- Quantity:
- Payment:

- Shipping:

Inventory:1,525
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TEA19032CABT/1J from NXP Semiconductors is a highly configurable secondary-side USB-PD 3.0 and QC4 controller for AC-DC SMPS, implementing CV/CC regulation with <2% voltage and current accuracy, integrated USB-PD PHY, and hardware-based protections including OVP, OTP, and OSP. It drives an external NMOS load switch via SW pin and supports PPS up to 20 V / 10 A in compact SO10 (SOT1437-1) package for high-power USB-C adapters.
For engineers reviewing the TEA19032CABT/1J datasheet, TEA19032CABT/1J pinout, TEA19032CABT/1J application, or TEA19032CABT/1J equivalent, key selection criteria include its 10-pin SO10 package, dual CC-line detection, MTP-programmable PDOs (up to 7, including 4 APDOs), 30 mW no-load power capability, and hardware-enforced fail-safe protections independent of MCU operation.
Technical Context
The TEA19032CABT/1J integrates a digital controller with embedded ROM/RAM/MTP memory, analog CV/CC loops using VSNS and ISNS inputs, and a dedicated USB-PD physical layer for Type-C v1.3 compliance. Its SW pin delivers VCC+6 V gate drive via internal charge pump, while DISCH pin enables fast Vbus discharge with hardware-monitored vSafe0V detection.
It implements all critical protections-including OVP, OTP (internal/external), OCP, OSUP, and CC-pin overvoltage-in hardware logic, ensuring fail-safe operation even during MCU lockup. The GPIO pin supports NTC temperature sensing with adaptive current sourcing (15/60/240 µA) and optional OTP, with measurement accuracy <5 °C across 0–120 °C using a 47 kΩ/4108-Beta NTC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Protocol Support | USB-PD 2.0/3.0 (including PPS), QC4, USB Type-C v1.3, unstructured VDMs for VID/PID/BDC programming |
| Output Range | 2.9 V to 21 V output voltage; 0.3 A to 5 A default max current; programmable via MTP up to 10 A |
| Regulation Accuracy | Better than ±2 % for both CV mode (12-bit DAC) and CC mode (10-bit DAC) |
| No-Load Power | <30 mW system-level no-load consumption meeting CoC Tier-2, EuP Lot6, DOE v6 |
| Protection Architecture | All protections except UVP implemented in hardware; latched or safe-restart behavior programmable in MTP |
| Package | SO10 (SOT1437-1), 3.9 mm body width, reflow/wave solder compatible |
| Temperature Sensing | Internal die sensor + external NTC via GPIO with <5 °C accuracy (0–120 °C, 47 kΩ/4108-Beta) |
Pinout & Package
TEA19032CABT/1J is housed in a 10-lead plastic small outline package (SO10, SOT1437-1) with 3.9 mm body width, optimized for high-density USB-C adapter designs and compatible with standard reflow and wave soldering processes.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Supply input | Secondary-side DC supply input (up to 21 V); powers internal circuits and triggers UVLO at ≈3 V |
| OPTO | Optocoupler driver | Drives optocoupler LED to regulate primary-side controller; replaces TL431 cathode function |
| GPIO | Configurable I/O | Selectable NTC sensing, NTC+OTP, supply output, or disabled; adaptive current sourcing for precision thermometry |
| ISNS | Current sense input | Accepts voltage drop across external shunt (2–22.5 mΩ); internal 50× gain amplifier with ≤2.5 V output limit |
| VSNS | Voltage sense input | Monitors output via resistor divider; sets CV reference matching MTP-programmed divider ratio (e.g., 1/8.325 for ≤20 V) |
| CC2 / CC1 | Type-C communication | Dual CC-line detection and USB-PD physical layer interface; hardware attach/detach and vSafe5V enforcement |
| DISCH | Fast discharge sink | Internal low-RON switch discharges Vbus to vSafe0V (<0.8 V); includes millisecond-interval sampling for hard reset compliance |
| GND | Ground reference | Analog/digital ground return; referenced by ISNS, VSNS, and internal ADCs |
| SW | NMOS gate driver | Charge-pump boosted output (VCC+6 V) directly drives external NMOS load switch gate |
Key Features
| Feature | Design Value |
|---|---|
| Hardware-enforced protections | All safety-critical protections (OVP, OTP, OCP, OSUP, CC-pin OV) implemented in analog/hardware logic-operational even if MCU stalls |
| Programmable power delivery | Up to 7 MTP-configurable PDOs, including 4 APDOs supporting PPS with 10 mV/20 mA resolution and cable compensation up to 200 mV/A |
| Ultra-low no-load power | System-level <30 mW no-load consumption achieved via minimal external components (≈15 BOM items) and intelligent circuit gating |
| Integrated load switch control | SW pin provides VCC+6 V gate drive; DISCH pin enables compliant Vbus ramp-down with hardware vSafe0V verification |
| Adaptive thermal monitoring | GPIO supports NTC sensing with three programmable current sources (15/60/240 µA) enabling <5 °C accuracy across 0–120 °C without calibration |
Applications
| Smartphone Fast Charging Adapter | Multi-Protocol Laptop Charger |
|---|---|
Use Scenario: Compact 65 W USB-C wall charger delivering QC4 and USB-PD 3.0 PPS to smartphones with dynamic voltage/current negotiation. IC Role / Device Role / Timing Role: Secondary-side protocol controller managing PDO selection, CC-line communication, CV/CC regulation, and hardware safety shutdown. Use Value: Enables single-chip support for QC4 + USB-PD 3.0 + PPS with <2% regulation accuracy and <30 mW no-load power-meeting global efficiency mandates. | Use Scenario: Universal laptop adapter supporting 15–20 V PPS profiles for diverse OEM notebooks requiring precise voltage stepping. IC Role / Device Role / Timing Role: Programmable secondary controller configuring up to 4 APDOs, real-time cable compensation, and adaptive thermal derating via GPIO-sensed connector temperature. Use Value: Delivers 20 V @ 5 A PPS with 10 mV resolution and hardware-enforced OVP/OTP, eliminating need for discrete protection ICs and reducing BOM count. |
| USB-C Power Bank Output Stage | Industrial USB-C PD Module |
Use Scenario: High-efficiency bi-directional power bank using TEA19032CABT/1J as DFP controller for regulated 5–20 V output to host devices. IC Role / Device Role / Timing Role: Secondary-side SMPS controller providing USB-PD negotiation, constant-current charging, and fast Vbus discharge on detach. Use Value: Hardware DISCH pin ensures vSafe0V compliance within USB-PD spec limits; SW pin directly drives NMOS switch-no external gate driver required. | Use Scenario: DIN-rail mounted USB-C PD module for industrial IoT gateways requiring robust overtemperature and open-supply protection. IC Role / Device Role / Timing Role: Fail-safe secondary controller with dual OTP (die + external NTC), OSUP, and hardware-latched protections for mission-critical deployments. Use Value: All critical protections operate independently of firmware-guaranteeing safe shutdown during MCU failure or brownout conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar USB-PD secondary-side controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STUSB4500QTR | Single-chip USB-PD 3.0 sink controller with integrated VBUS switch; lacks PPS support and external NMOS gate drive | Targeted at lower-power (≤30 W) sink-only applications; no CV/CC regulation capability for SMPS feedback | Choose STUSB4500QTR only for simple sink implementations without SMPS control requirements |
| MPQ4282-AEC1 | Automotive-grade USB-PD 3.0 controller with AEC-Q100 qualification; requires external optocoupler and separate load switch driver | Designed for automotive infotainment power delivery; higher cost and larger footprint due to external component dependencies | Prefer MPQ4282-AEC1 only when AEC-Q100 compliance is mandatory and automotive temperature range (-40°C to 125°C) is required |
Compared with STUSB4500QTR and MPQ4282-AEC1, TEA19032CABT/1J uniquely combines full-source-side SMPS control (CV/CC), PPS support, hardware-enforced protections, and direct NMOS gate drive in a 10-pin SO10 package-enabling compact, high-efficiency, multi-protocol chargers with minimal external components.
Availability
TEA19032CABT/1J is available at Aetrix Electronics and suitable for high-power USB-C smartphone adapters, universal laptop chargers, and industrial USB-PD modules requiring stable component supply, long-term lifecycle support, and compliance with CoC Tier-2 and DOE v6 efficiency standards.
Supply support for TEA19032CABT/1J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and consumer applications, with deep expertise in power management and USB ecosystem integration.
The TEA19032CABT/1J belongs to NXP's TEA190xx smart-charging controller family, designed specifically to enable compact, high-efficiency, multi-protocol USB-C power adapters meeting stringent global energy regulations and safety standards.
FAQ
What USB-PD and QC protocols does the TEA19032CABT/1J support?
The TEA19032CABT/1J supports USB-PD 2.0 and 3.0-including Programmable Power Supply (PPS)-USB Type-C v1.3, and Qualcomm QuickCharge 4 (QC4). It implements the full DFP stack with hardware-based CC-line detection, VDM handling for VID/PID programming, and up to seven MTP-configurable PDOs, four of which can be APDOs for PPS operation.
How does the TEA19032CABT/1J achieve <30 mW no-load power?
The TEA19032CABT/1J achieves <30 mW system-level no-load power through ultra-low quiescent current design, intelligent circuit gating during unattached state, and minimal external component count (≈15 parts). Its hardware-controlled DISCH and SW pins eliminate leakage paths, while the GPIO pin's adaptive current sourcing avoids continuous bias current-enabling compliance with CoC Tier-2 and DOE v6 efficiency standards.
Can the TEA19032CABT/1J drive an external NMOS load switch directly?
Yes, the TEA19032CABT/1J drives an external NMOS load switch directly via its SW pin, which outputs VCC+6 V using an internal charge pump. This eliminates the need for an external gate driver. When VCC drops below UVLO (≈3 V), the SW pin is actively held low to ensure the NMOS remains off-providing fail-safe isolation during fault conditions.
What protections are implemented in hardware versus firmware on the TEA19032CABT/1J?
All critical protections-including OVP, OTP (internal and external), OCP, OSUP, and CC-pin overvoltage-are implemented in hardware on the TEA19032CABT/1J and remain fully functional even if the embedded MCU locks up. Only undervoltage protection (UVP) is implemented in firmware; all other protections respond within defined filter times (e.g., 30 µs for OVP, 20 ms for OCP) and can be configured as latched or safe-restart in MTP memory.
How is temperature monitored using the GPIO pin on the TEA19032CABT/1J?
The GPIO pin on the TEA19032CABT/1J supports NTC-based temperature sensing with three programmable current sources (15/60/240 µA) that adaptively bias a 47 kΩ/4108-Beta NTC. The internal ADC measures the resulting voltage, enabling <5 °C accuracy from 0 °C to >120 °C. When configured for NTC+OTP, hardware-triggered shutdown occurs if the measured temperature exceeds the MTP-programmed threshold.
TEA19032CABT/1J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 10-SOIC (0.154", 3.90mm Width)
- Programmable:
- Not Verified
- Protocol:
- USB
- Function:
- Controller
- Interface:
- USB
- Standards:
- USB 2.0, USB 3.0
- Voltage - Supply:
- 2.9V ~ 21V
- Current - Supply:
- 3mA
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Supplier Device Package:
- 10-SO
- Grade:
- -
- Qualification:
- -
TEA19032CABT/1J FAQ
1.How can I place an order for TEA19032CABT/1J through Aetrix?
Please submit a Request for Quotation (RFQ) for TEA19032CABT/1J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TEA19032CABT/1J reliable?
The price and inventory of TEA19032CABT/1J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TEA19032CABT/1J is usually 5 days.
3.What payment methods are accepted for TEA19032CABT/1J?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TEA19032CABT/1J transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TEA19032CABT/1J?
TEA19032CABT/1J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TEA19032CABT/1J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TEA19032CABT/1J?
For technical support, including TEA19032CABT/1J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TEA19032CABT/1J requirements.
6.How does Aetrix verify that TEA19032CABT/1J is sourced from the original manufacturer or authorized distributors?
All TEA19032CABT/1J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TEA19032CABT/1J meets industry standards.
7.What is the process for return or replacement of TEA19032CABT/1J?
All TEA19032CABT/1J units undergo pre-shipment inspection (PSI). If there is an issue with TEA19032CABT/1J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TEA19032CABT/1J part is unused and in its original packaging.
Return procedure for TEA19032CABT/1J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TEA19032CABT/1J Tags

-
PTN5150AHXMP
NXP Semiconductors

-
USB3740B-AI9-TR
Microchip Technology

-
USB3740B-AI2-TR
Microchip Technology

-
USB3300-EZK-TR
Microchip Technology

-
USB3300-EZK
Microchip Technology

-
FUSB340TMX
onsemi

-
FUSB302BMPX
onsemi

-
DP83826IRHBR
Texas Instruments

-
MCP2518FDT-E/QBB
Microchip Technology

-
FUSB302MPX
onsemi

-
MCP2518FDT-E/SL
Microchip Technology

-
FT260Q-R
FTDI, Future Technology Devices International Ltd
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

