NXP Semiconductors TEA19051BACTK/1J
- Part No.:
- TEA19051BACTK/1J
- Manufacturer:
- NXP Semiconductors
- Category:
- Controllers
- Package:
- 16-VDFN Exposed Pad
- Datasheet:
-
TEA19051BACTK/1J.pdf
- Description:
- IC SMPS CTRLR SMART CHRG HVSON16
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TEA19051BACTK/1J from NXP Semiconductors is a secondary-side USB-PD 3.0/PPS and QC4+ smart-charging controller for AC-DC SMPS, supporting CV/CC regulation with ±2 % output voltage and current accuracy, 2.9 V–21 V programmable output range, and ultra-low no-load power (<30 mW). It integrates USB-PD PHY, charge pump gate driver (SW pin), fast discharge (DISCH), and dual GPIO-based NTC temperature sensing for smartphone/tablet adapters.
For engineers reviewing the TEA19051BACTK/1J datasheet, TEA19051BACTK/1J pinout, TEA19051BACTK/1J application, or TEA19051BACTK/1J equivalent, key selection criteria include USB-PD 3.0 + PPS compliance, hardware-enforced protections (OTP/OVP/OCP/OSP), HVSON16 package compatibility, and MTP-configurable PDOs, cable compensation, and GPIO functions - all critical for certified high-power USB-C chargers.
Technical Context
The TEA19051BACTK/1J implements a digitally controlled analog CV/CC loop using internal 12-bit DAC (voltage) and 10-bit DAC (current), with continuous ADC-based measurement of VSNS and ISNS inputs. Its USB-PD 3.0 stack supports up to seven PDOs - four configurable as PPS - and integrates hardware-level attach/detach detection on CC1/CC2 pins per USB Type-C v1.3.
Protection logic resides in dedicated hardware blocks independent of firmware execution, enabling latched or safe-restart response for OTP, OVP, UVP, OCP, OSP, and soft-short detection on CC/DP/DM/Vbus. The SW pin drives an external NMOS load switch via integrated charge pump (VCC + 6 V), while DISCH provides controlled Vbus ramp-down meeting USB-PD vSafe0V requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage Range | 2.9 V to 21 V; programmable via USB-PD or QC protocols with hardware-enforced OVP/UVP thresholds |
| CV/CC Accuracy | Better than ±2 % at full load; achieved via 12-bit voltage DAC and 10-bit current DAC with continuous ADC monitoring |
| No-Load Power | <30 mW system-level; enabled by minimal external components (≈15) and adaptive circuit enablement during unattached state |
| Protocol Support | USB-PD 2.0/3.0 + PPS, QC2.0/QC3.0/QC4+, BC1.2, USB Type-C v1.3; all implemented in hardware/firmware with MTP-configurable PDOs |
| Package | HVSON16 (SOT1308-1); 3.5 × 5.5 × 0.85 mm body; reflow-solderable with exposed die pad (EDP) for thermal management |
| Protections | Hardware-implemented OTP (internal + 2 external), OVP, UVP, OCP, OSP, OSUP, OGP, CC/DP/DM pin overvoltage, and soft-short detection |
| GPIO Functionality | Two pins (GPIO1/GPIO2) configurable via MTP as NTC thermistor interface (±5 °C accuracy), NTC+OTP, supply output, or disabled |
Pinout & Package
HVSON16 package (SOT1308-1) with 3.5 × 5.5 × 0.85 mm footprint and exposed die pad (EDP) for thermal conduction. Pin 17 (EDP) must be soldered to PCB ground plane for optimal thermal performance and electrical stability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Supply input | Secondary-side DC supply (up to 21 V); powers internal circuits and enables UVLO-based load switch control |
| OPTO | Optocoupler driver output | Replaces TL431 cathode; drives optocoupler LED to regulate primary-side controller via feedback loop |
| SGND | Sense ground reference | Dedicated low-noise ground for ISNS and VSNS; requires separate PCB trace from power ground |
| ISNS | Current sense input | Accepts mΩ-shunt voltage drop; internal 50× amplifier enables precise CC-mode regulation and OCP |
| VSNS | Voltage sense input | Connects to resistor divider from VCC; sets CV reference point matching MTP-programmed divider ratio |
| SCL/SDA | I²C interface | Supports MTP programming, VDM exchange, and real-time parameter readback (e.g., temperature, PDO status) |
| CC1/CC2 | Type-C configuration channel | Hardware-based attach/detach detection and USB-PD communication; compliant with USB Type-C v1.3 |
| DP/DM | QC/BC data lines | Enable Qualcomm QuickCharge 2.0/3.0/4+ and Battery Charging 1.2 protocol negotiation |
| DISCH | Fast discharge sink | Internal low-RON switch discharges Vbus through external resistor to meet USB-PD vSafe0V (<0.8 V) requirement |
| SW | NMOS gate driver | Charge-pump boosted output (VCC + 6 V) directly drives external NMOS load switch gate |
| GND | Power ground | Main return path; isolated from SGND to prevent noise coupling into precision sense paths |
Key Features
| Feature | Design Value |
|---|---|
| Integrated USB-PD 3.0 + PPS PHY | Enables certified 100 W charging with dynamic voltage/current adjustment (20 mV/50 mA steps) without external transceiver |
| Hardware-enforced safety protections | All critical protections (OTP/OVP/OCP/OSP) implemented in analog/hardware logic - functional even if MCU stalls |
| MTP-configurable PDOs and cable compensation | Up to 7 PDOs (4 PPS-capable); cable compensation programmable per PDO (0–200 mV/A) to maintain terminal voltage under load |
| Dual NTC temperature sensing | GPIO1/GPIO2 support adaptive-current NTC biasing for accurate adapter/cable connector temperature monitoring (±5 °C, 0–120 °C) |
| Ultra-low system no-load power | <30 mW achieved via intelligent circuit gating, 20 µA standby current, and optimized sleep modes during unattached state |
Applications
| Smartphone Fast Charging Adapter | Tablet USB-C Wall Charger |
|---|---|
Use Scenario: 45 W–65 W compact wall charger delivering PPS-adjusted 9 V/3 A or 15 V/3 A to flagship smartphones with thermal throttling awareness. IC Role / Device Role / Timing Role: Secondary-side USB-PD 3.0 + QC4+ controller managing CV/CC regulation, Vbus discharge, and real-time temperature reporting via VDMs. Use Value: Enables CoC Tier-2/EuP Lot 6 compliance with <30 mW no-load power and hardware-safe OVP/OTP response within 10 µs - critical for UL62368-1 certification. |
Use Scenario: Multi-voltage USB-C charger supporting 5 V/3 A, 9 V/3 A, 15 V/3 A, and 20 V/3.25 A profiles for tablets requiring precise cable compensation across 1–2 m cables. IC Role / Device Role / Timing Role: Programmable SMPS controller executing USB-PD contract negotiation, dynamic PDO selection, and adaptive cable compensation based on ISNS-measured current. Use Value: Delivers ±2 % output accuracy across full load range using integrated 12-bit DAC and continuous ADC sampling - eliminating need for post-regulation LDOs. |
| Multi-Protocol Laptop Dock Charger | USB-PD Certified Power Brick |
Use Scenario: 100 W dock-integrated charger supporting simultaneous USB-PD 3.0 PPS (for laptop CPU/GPU power states) and BC1.2 legacy device charging. IC Role / Device Role / Timing Role: Dual-role controller handling DP/DM-based QC/BC negotiation alongside CC1/CC2-based USB-PD 3.0 messaging and VDM-based vendor ID exchange. Use Value: Integrates discover identification (VID/PID/BCD) and MTP-stored power profile data - required for USB-IF PD3.0 certification and interoperability testing. |
Use Scenario: UL/CE-certified standalone power brick targeting USB-IF PD compliance with mandatory hard reset, vSafe0V, and source capability advertisement. IC Role / Device Role / Timing Role: Hardware-verified USB-PD DFP controller implementing CC-line pull-up currents, vSafe5V recovery, and DISCH-driven vSafe0V discharge per spec timing. Use Value: Meets USB-PD 3.0 physical layer requirements without external level shifters or discrete protection ICs - reducing BOM count by ≥3 components. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar USB-PD + QC secondary-side controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STUSB4500QTR | Single-protocol USB-PD 3.0 controller; no QC/BC support; requires external MCU for PPS sequencing | Limited to USB-C-only devices; cannot replace QC2.0/3.0 legacy compatibility requirements | Select when only USB-PD 3.0 + PPS is needed and cost-sensitive BOM allows external microcontroller integration |
| MPQ4282-AEC1 | Automotive-grade USB-PD 3.0 controller with AEC-Q100 qualification; lacks QC4+/BC1.2 support and GPIO-based NTC sensing | Targeted for vehicle-mounted chargers; not optimized for consumer adapter efficiency or thermal monitoring | Choose for automotive infotainment or telematics power supplies requiring ASIL-B compliance and extended temperature range |
Compared with STUSB4500QTR and MPQ4282-AEC1, the TEA19051BACTK/1J uniquely combines USB-PD 3.0 + PPS, QC4+, and BC1.2 in one hardware-enforced controller with integrated NTC sensing and <30 mW no-load operation - making it the only option for compact, multi-protocol, thermally aware consumer adapters requiring full USB-IF certification.
Availability
TEA19051BACTK/1J is available at Aetrix Electronics and suitable for USB-C smartphone fast chargers, tablet wall adapters, and multi-protocol laptop docks requiring stable component supply, long-term lifecycle support, and full USB-IF PD3.0 certification readiness.
Supply support for TEA19051BACTK/1J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and consumer applications, with core expertise in power management and USB ecosystem ICs.
The TEA19051BACTK/1J belongs to NXP's TEA190xx smart-charging controller family, designed specifically for high-efficiency, multi-protocol AC-DC adapters targeting USB-IF certification, CoC Tier-2 compliance, and thermal-aware fast charging.
FAQ
What USB-PD and QC protocols does the TEA19051BACTK/1J support?
The TEA19051BACTK/1J supports USB-PD 2.0 and 3.0 including Programmable Power Supply (PPS), Qualcomm QuickCharge 2.0, 3.0, and 4+, plus Battery Charging 1.2 (BC1.2) and USB Type-C v1.3. All protocols are implemented in hardware/firmware with MTP-configurable PDOs and VDM support - enabling full USB-IF PD3.0 certification when QC2.0/QC3.0 are disabled per specification.
How does the TEA19051BACTK/1J achieve <30 mW no-load power?
The TEA19051BACTK/1J achieves <30 mW system-level no-load power through hardware-gated circuit enablement during unattached state, adaptive current sources for GPIO NTC biasing, and optimized low-power modes - all verified per CoC Tier-2 and EuP Lot 6 standards. Its ≈15-component BOM and single-optocoupler feedback further minimize quiescent losses.
What protections are implemented in hardware versus firmware on the TEA19051BACTK/1J?
Overtemperature (OTP), overvoltage (OVP), undervoltage (UVP), overcurrent (OCP), output short (OSP), open-supply (OSUP), open-ground (OGP), and CC/DP/DM pin overvoltage protections are implemented in dedicated hardware blocks on the TEA19051BACTK/1J - ensuring fail-safe operation even if the embedded MCU stalls. Only UVP can be software-configured; all others respond in <10 µs without firmware dependency.
Can the TEA19051BACTK/1J drive an external NMOS load switch directly?
Yes, the TEA19051BACTK/1J drives an external NMOS load switch directly via its SW pin, which outputs a charge-pump boosted voltage of VCC + 6 V. This eliminates the need for external level-shifters or gate drivers. The SW pin remains low when VCC is below UVLO or disconnected, ensuring the load switch stays off during fault or startup conditions.
What is the role of the DISCH pin on the TEA19051BACTK/1J?
The DISCH pin on the TEA19051BACTK/1J provides a hardware-controlled, low-ohmic discharge path for Vbus to meet USB-PD vSafe0V requirements (<0.8 V after hard reset). An internal switch activates with precise timing, and an external series resistor limits peak current. The IC monitors actual Vbus during millisecond-scale discharge pulses to terminate discharge once vSafe0V is confirmed.
TEA19051BACTK/1J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 16-VDFN Exposed Pad
- Programmable:
- Not Verified
- Protocol:
- USB
- Function:
- Controller
- Interface:
- USB
- Standards:
- USB 2.0, USB 3.0
- Voltage - Supply:
- 2.9V ~ 21V
- Current - Supply:
- 3mA
- Operating Temperature:
- -20°C ~ 105°C (TJ)
- Supplier Device Package:
- 16-HVSON (3.5x5.5)
- Grade:
- -
- Qualification:
- -
TEA19051BACTK/1J FAQ
1.How can I place an order for TEA19051BACTK/1J through Aetrix?
Please submit a Request for Quotation (RFQ) for TEA19051BACTK/1J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TEA19051BACTK/1J reliable?
The price and inventory of TEA19051BACTK/1J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TEA19051BACTK/1J is usually 5 days.
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TEA19051BACTK/1J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TEA19051BACTK/1J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TEA19051BACTK/1J?
For technical support, including TEA19051BACTK/1J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TEA19051BACTK/1J requirements.
6.How does Aetrix verify that TEA19051BACTK/1J is sourced from the original manufacturer or authorized distributors?
All TEA19051BACTK/1J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TEA19051BACTK/1J meets industry standards.
7.What is the process for return or replacement of TEA19051BACTK/1J?
All TEA19051BACTK/1J units undergo pre-shipment inspection (PSI). If there is an issue with TEA19051BACTK/1J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TEA19051BACTK/1J part is unused and in its original packaging.
Return procedure for TEA19051BACTK/1J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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