My Inquiry
My Account
NXP Semiconductors TEA19051BAGTK/1J
- Part No.:
- TEA19051BAGTK/1J
- Manufacturer:
- NXP Semiconductors
- Category:
- Controllers
- Package:
- 16-VDFN Exposed Pad
- Datasheet:
-
TEA19051BAGTK/1J.pdf
- Description:
- SMARTCHARG PROTOC CONTR QC4
- Quantity:
- Payment:
- Shipping:
Inventory:1,566
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TEA19051BAGTK/1J from NXP Semiconductors is a secondary-side USB-PD 3.0 and QC4+ controller IC for AC-DC SMPS, supporting programmable power supply (PPS), constant voltage (±2 % accuracy), constant current (±2 % full-load accuracy), and integrated NMOS gate drive via SW pin. It enables ultra-low no-load power (<30 mW) in compact USB-C chargers.
For engineers reviewing the TEA19051BAGTK/1J datasheet, TEA19051BAGTK/1J pinout, TEA19051BAGTK/1J application, or TEA19051BAGTK/1J equivalent, key selection criteria include USB-PD 3.0 + PPS compliance, dual CC/DP-DM protocol support, hardware-enforced protections (OTP/OVP/OCP/OSP), MTP-configurable PDOs, and HVSON16 package compatibility with reflow soldering.
Technical Context
The TEA19051BAGTK/1J implements a digitally controlled analog CV/CC loop with 12-bit DAC (voltage) and 10-bit DAC (current), using VSNS and ISNS inputs for real-time feedback. Its embedded MCU executes USB-PD 3.0 and QC4+ state machines while offloading protocol timing-critical tasks to dedicated hardware blocks including USB-PD PHY, Type-C condet, and VDM parser.
All safety protections - including adaptive OVP/UVP, OTP (internal + two external), OSP, and soft-short detection on CC1/CC2 - are implemented in hardware with latched or safe-restart response modes. The charge pump-driven SW pin delivers VCC + 6 V gate drive, and DISCH pin enables vSafe0V-compliant output discharge via external resistor-limited sink.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Protocol Support | USB-PD 2.0/3.0 with PPS, QC2.0/QC3.0/QC4+, BC1.2, USB Type-C v1.3 |
| Output Voltage Range | 2.9 V to 21 V; programmable via MTP with up to 7 PDOs including 4 PPS profiles |
| CV/CC Accuracy | Better than ±2 % for both voltage regulation and full-load current regulation |
| No-Load Power | <30 mW system-level consumption, meeting CoC Tier-2, EuP Lot 6, DOE VI |
| Protection Architecture | Hardware-only OTP/OVP/UVP/OCP/OSP/OSUP/OGP with configurable latched/safe-restart behavior |
| Interface Pins | CC1/CC2 for USB-PD, DP/DM for QC/BC1.2, SCL/SDA for I²C configuration, GPIO1/GPIO2 for NTC temperature sensing |
| Package | HVSON16 (SOT1308-1), 3.5 × 5.5 × 0.85 mm, lead-free, reflow-compatible |
Pinout & Package
HVSON16 package (SOT1308-1) with exposed die pad (EDP) for thermal dissipation; 16-pin layout optimized for minimal external component count and high-density USB-C adapter designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Supply input | Secondary-side DC supply (up to 21 V); powers internal circuits and enables UVLO-based startup sequencing |
| OPTO | Optocoupler driver output | Replaces TL431 cathode; drives optocoupler LED to regulate primary-side controller via feedback loop |
| SGND | Sense ground reference | Isolated ground return for ISNS and VSNS to prevent noise coupling into precision ADC paths |
| GPIO1 / GPIO2 | Configurable I/O | Support NTC thermistor interface (adapter/cable temp), OTP trigger, or I²C slave supply - all set via MTP |
| ISNS | Current sense input | Accepts mΩ-shunt voltage (gain ×50); enables CC mode and OCP with 0.02 mΩ resolution and MTP-calibrated scaling |
| VSNS | Voltage sense input | High-impedance CV feedback node; requires precise resistor divider matching MTP-programmed ratio (e.g., 1/8.325 for ≤20 V) |
| SCL / SDA | I²C interface | Used for factory programming, field updates, and runtime parameter readback (VID/PID, temperature, PDO status) |
| DM / DP | QC/BC data lines | Enable Qualcomm QuickCharge and Battery Charging 1.2 negotiation; must be shorted for BC1.2 compliance |
| CC1 / CC2 | Type-C communication | Hardware-based attach/detach detection and USB-PD packet exchange per USB Type-C v1.3 spec |
| DISCH | Fast discharge sink | Internal low-RON switch discharges Vbus to <0.8 V within USB-PD vSafe0V limits using external current-limiting resistor |
| GND | Power ground | Main return path for load switch, internal logic, and protection circuitry |
| SW | NMOS gate driver | Charge-pump boosted (VCC + 6 V) output directly drives external NMOS load switch without external level shifter |
| EDP | Exposed die pad | Thermal pad connected to internal die; must be soldered to PCB copper for thermal management |
Key Features
| Feature | Design Value |
|---|---|
| Dual-protocol negotiation engine | Simultaneous hardware support for USB-PD 3.0 (including PPS) and QC4+, with MTP-selectable priority and conflict resolution |
| Hardware-safeguarded protections | All critical protections (OTP/OVP/OCP/OSP) implemented in analog/hardware domain - remain active even if MCU freezes |
| Programmable cable compensation | MTP-configurable up to 200 mV/A, applied per PDO to maintain target voltage at device connector under load |
| Integrated charge pump & discharge | VCC + 6 V SW drive eliminates external level shifter; DISCH pin meets USB-PD vSafe0V timing with adaptive voltage sampling |
| Low-component-count architecture | Only one optocoupler required for primary-side control; ≈15 total external components for full-featured USB-C SMPS |
Applications
| Smartphone Fast Charging Adapter | Multi-Protocol Tablet Charger |
|---|---|
Use Scenario: 45 W USB-C wall charger delivering 9 V/3 A (QC3.0) or 15 V/3 A (USB-PD 3.0 PPS) to flagship smartphones. IC Role / Device Role / Timing Role: Secondary-side protocol controller managing V/I negotiation, CV/CC regulation, and hardware safety enforcement. Use Value: Enables single-chip support for QC4+ and USB-PD 3.0 with PPS, reducing BOM count while maintaining ±2 % output accuracy and <30 mW no-load power. | Use Scenario: 65 W universal travel adapter powering tablets across USB-PD, QC3.0, and legacy BC1.2 devices. IC Role / Device Role / Timing Role: Central SMPS controller coordinating optocoupler feedback, NMOS load switching, and dual-path (CC/DP-DM) protocol arbitration. Use Value: Delivers programmable PDOs (including 4 PPS profiles), adaptive cable compensation, and hardware OTP/OVP - ensuring safe multi-voltage operation without firmware dependency. |
| Laptop Docking Station Power Module | USB-C Automotive In-Car Charger |
Use Scenario: Dock-integrated 100 W PD EPR-capable power delivery module supplying laptop + peripherals via single USB-C port. IC Role / Device Role / Timing Role: Secondary-side PD controller handling extended power range negotiation, real-time current/voltage telemetry, and fast discharge during hard reset. Use Value: Supports up to 21 V output with MTP-configurable PDOs and hardware-enforced OCP/OSP - enabling robust 100 W operation with <30 mW standby draw. | Use Scenario: 30 W in-vehicle USB-C charger adapting to varying input (9–16 V automotive rail) while delivering stable 9 V/3 A QC3.0 output. IC Role / Device Role / Timing Role: Isolated secondary-side controller interfacing with primary QR controller (e.g., TEA1936x) and SR driver (e.g., TEA1995x). Use Value: Integrates UVLO tracking, GPIO-based NTC temperature monitoring, and hardware UVP/OVP - ensuring safe operation across wide automotive voltage transients. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar USB-PD + QC secondary-side controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STUSB4760QTR | Single-protocol USB-PD 3.0 controller only; no QC2.0/3.0/4+ or BC1.2 support; requires external MCU for PPS control | Targeted at pure USB-C PD applications without Qualcomm ecosystem requirements | Select when USB-PD 3.0 compliance is sole requirement and QC/BC legacy support is unnecessary |
| MPQ4282-AEC1 | Automotive-grade USB-PD 3.0 + QC4+ controller; AEC-Q100 qualified; supports 40 V max VCC; no MTP memory for field reconfiguration | Designed for automotive environments with extended temperature and EMC requirements | Choose for in-vehicle applications requiring AEC-Q100 qualification and higher input voltage tolerance |
Compared with STUSB4760QTR and MPQ4282-AEC1, the TEA19051BAGTK/1J uniquely combines USB-PD 3.0 + PPS, QC4+, and BC1.2 in a single MTP-programmable IC with hardware safety enforcement, making it optimal for cost-sensitive, high-volume consumer USB-C adapters requiring multi-protocol interoperability and <30 mW no-load performance.
Availability
TEA19051BAGTK/1J is available at Aetrix Electronics and suitable for USB-C fast charging adapters, multi-protocol tablet chargers, and laptop docking station power modules requiring stable component supply, long-term lifecycle assurance, and compliance with CoC Tier-2 and DOE VI efficiency standards.
Supply support for TEA19051BAGTK/1J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer electronics.
The TEA19051BAGTK/1J belongs to NXP's TEA19xxx family of highly integrated secondary-side SMPS controllers, designed specifically to replace discrete TL431-based feedback systems while adding USB-PD, QC, and BC protocol intelligence with hardware-enforced safety.
FAQ
What protocols does the TEA19051BAGTK/1J support out of the box?
The TEA19051BAGTK/1J natively supports USB-PD 2.0/3.0 (including PPS), Qualcomm QuickCharge 2.0/3.0/4+, and Battery Charging 1.2 - all implemented in hardware with MTP-configurable enable/disable settings. No external MCU is required for basic protocol operation, and factory-programmed versions ship with specific PDO sets preloaded in non-volatile memory.
How does the TEA19051BAGTK/1J achieve <30 mW no-load power consumption?
The TEA19051BAGTK/1J achieves <30 mW system-level no-load power through ultra-low quiescent current design, dynamic circuit activation (only essential blocks powered before attach), and hardware-controlled load switch gating. Its integrated charge pump and DISCH pin minimize leakage paths, while MTP-configurable sleep modes further reduce idle current - enabling compliance with CoC Tier-2 and DOE VI efficiency regulations.
Can the TEA19051BAGTK/1J be used with existing TL431-based SMPS designs?
Yes - the TEA19051BAGTK/1J is architecturally compatible with TL431-based feedback topologies: VSNS replaces REF, OPTO replaces cathode, and GND replaces anode. However, redesign is required to integrate CC1/CC2, DP/DM, and GPIO pins; the TEA19051BAGTK/1J also mandates an external NMOS load switch and current-sense resistor, replacing the TL431's shunt function with active CV/CC regulation and protocol awareness.
What protection features are implemented in hardware versus firmware on the TEA19051BAGTK/1J?
All critical protections - overtemperature (OTP), overvoltage (OVP), undervoltage (UVP), overcurrent (OCP), output short (OSP), open-supply (OSUP), and open-ground (OGP) - are implemented in hardware and remain fully functional even if the embedded MCU locks up. Only non-safety-critical functions like MTP configuration, VDM processing, and PDO selection rely on firmware execution.
Does the TEA19051BAGTK/1J require external components for USB-PD communication?
No - the TEA19051BAGTK/1J integrates a complete USB-PD physical layer (PHY), Type-C connection detection (condet), and protocol engine. External components needed are limited to passive termination resistors on CC1/CC2 (per USB Type-C spec), an NMOS load switch, current-sense resistor, voltage-divider network for VSNS, and optocoupler - no external transceivers or level shifters are required for USB-PD 3.0 or QC4+ operation.
TEA19051BAGTK/1J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 16-VDFN Exposed Pad
- Programmable:
- Not Verified
- Protocol:
- USB
- Function:
- Controller
- Interface:
- USB
- Standards:
- USB 2.0, USB 3.0
- Voltage - Supply:
- 2.9V ~ 21V
- Current - Supply:
- 3mA
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Supplier Device Package:
- 16-HVSON (3.5x5.5)
- Grade:
- -
- Qualification:
- -
TEA19051BAGTK/1J FAQ
1.How can I place an order for TEA19051BAGTK/1J through Aetrix?
Please submit a Request for Quotation (RFQ) for TEA19051BAGTK/1J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TEA19051BAGTK/1J reliable?
The price and inventory of TEA19051BAGTK/1J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TEA19051BAGTK/1J is usually 5 days.
3.What payment methods are accepted for TEA19051BAGTK/1J?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TEA19051BAGTK/1J transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TEA19051BAGTK/1J?
TEA19051BAGTK/1J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TEA19051BAGTK/1J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TEA19051BAGTK/1J?
For technical support, including TEA19051BAGTK/1J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TEA19051BAGTK/1J requirements.
6.How does Aetrix verify that TEA19051BAGTK/1J is sourced from the original manufacturer or authorized distributors?
All TEA19051BAGTK/1J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TEA19051BAGTK/1J meets industry standards.
7.What is the process for return or replacement of TEA19051BAGTK/1J?
All TEA19051BAGTK/1J units undergo pre-shipment inspection (PSI). If there is an issue with TEA19051BAGTK/1J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TEA19051BAGTK/1J part is unused and in its original packaging.
Return procedure for TEA19051BAGTK/1J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TEA19051BAGTK/1J Tags
-
PTN5150AHXMP
NXP Semiconductors
-
USB3740B-AI9-TR
Microchip Technology
-
USB3740B-AI2-TR
Microchip Technology
-
USB3300-EZK-TR
Microchip Technology
-
USB3300-EZK
Microchip Technology
-
FUSB340TMX
onsemi
-
FUSB302BMPX
onsemi
-
DP83826IRHBR
Texas Instruments
-
MCP2518FDT-E/QBB
Microchip Technology
-
FUSB302MPX
onsemi
-
MCP2518FDT-E/SL
Microchip Technology
-
FT260Q-R
FTDI, Future Technology Devices International Ltd
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
