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NXP Semiconductors TEA19051BAMTK/1J

Part No.:
TEA19051BAMTK/1J
Manufacturer:
NXP Semiconductors
Category:
Controllers
Package:
-
Datasheet:
AetrixTEA19051BAMTK/1J.pdf
Description:
SMARTCHARG PROTOC CONTR QC4
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Payment
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Inventory:20,000

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Product details

Overview

TEA19051BAMTK/1J from NXP Semiconductors is a USB-PD 3.0 and QC4+ secondary-side SMPS controller in HVSON16 (SOT1308-1) package, delivering 2% CV/CC regulation accuracy, <30 mW no-load power, and integrated USB-PD PHY, charge pump for NMOS gate drive, and fast DISCH functionality. It enables compact, CoC Tier-2/EuP Lot6-compliant USB-C chargers with programmable PPS and cable compensation.

For engineers reviewing the TEA19051BAMTK/1J datasheet, TEA19051BAMTK/1J pinout, TEA19051BAMTK/1J application, or TEA19051BAMTK/1J equivalent, key selection considerations include its hardware-enforced protections (OTP, OVP, OSP), MTP-programmable PDOs (up to 7, including 4 PPS), dual GPIO temperature sensing, and single-optocoupler feedback architecture interfacing with TEA193x primary and TEA199x SR controllers.

Technical Context

The TEA19051BAMTK/1J implements a digitally controlled analog CV/CC loop with 12-bit DAC (voltage) and 10-bit DAC (current), where VSNS and ISNS pins interface with external resistor dividers and sense resistors (2–22.5 mΩ) to regulate output voltage (2.9–21 V) and current with hardware-backed adaptive protection logic. Its embedded MCU executes protocol stacks (USB-PD 2.0/3.0, QC2.0/3.0/4+, BC1.2) while maintaining independent hardware safety monitors.

It integrates a USB-PD physical layer with CC1/CC2 detection and communication, DP/DM support for QC/Battery Charging, and dedicated SW (NMOS gate drive at VCC + 6 V) and DISCH (fast Vbus discharge with vSafe0V compliance) terminals. All protections - except UVP - are implemented in hardware with latched or safe-restart behavior, ensuring fail-safe operation even during MCU lockup.

Key Specifications

Parameter Value and Actual Design Meaning
Output Voltage Range 2.9 V to 21 V; supports USB-PD PPS and QC4+ variable profiles with MTP-configurable PDOs.
CV/CC Accuracy Better than ±2 %; enables precise regulation for USB-C PD compliance and smartphone fast-charge certification.
No-Load Power <30 mW system-level; meets CoC Tier-2, EuP Lot6, and DOE v6 efficiency requirements.
Protocol Support USB-PD 2.0/3.0 (including PPS), QC2.0/QC3.0/QC4+, BC1.2, and unstructured VDMs for VID/PID/MTP programming.
Protection Architecture Hardware-enforced OTP (internal + 2 external), OVP, OSP, OCP, UVLO, OSUP, OGP, and soft-short protection on CC/DP/DM/Vbus.
Package & Pin Count HVSON16 (SOT1308-1); 3.5 × 5.5 × 0.85 mm; 16-pin footprint with exposed die pad (EDP) for thermal management.
MTP Memory Non-volatile multi-time programmable memory storing up to 7 PDOs, cable compensation, GPIO functions, OTP thresholds, and vendor IDs.

Pinout & Package

HVSON16 package (SOT1308-1), 3.5 × 5.5 × 0.85 mm body size, leadless, reflow-solderable, with exposed die pad (EDP) for thermal conduction.

Pin/Terminal Circuit Role Design Meaning
VCC Supply input Secondary-side DC supply (up to 21 V); powers internal circuits and triggers UVLO/OVP based on programmed % of output voltage.
OPTO Optocoupler driver output Replaces TL431 cathode; drives optocoupler LED to regulate primary-side controller via single feedback loop.
SGND Sense ground reference Isolated ground return for ISNS and VSNS to prevent noise coupling into precision analog loops.
GPIO1 / GPIO2 Configurable I/O Support NTC thermistor readout (adapter/cable temp), NTC+OTP, or I2C slave supply; each with adaptive current sourcing.
ISNS Current sense input Accepts mV-level drop across 2–22.5 mΩ sense resistor; internal 50× amplifier feeds CC loop with 10-bit DAC control.
VSNS Voltage sense input Monitors scaled output voltage via resistor divider; closed-loop CV regulation uses 12-bit DAC and internal 1.22 V reference.
SCL / SDA I²C interface Allows host MCU configuration of MTP parameters, real-time telemetry (temp, V/I), and VDM-based vendor ID discovery.
CC1 / CC2 USB-C configuration channel Hardware-detected attach/detach; bidirectional USB-PD communication PHY with soft-short protection and vSafe5V enforcement.
DP / DM Legacy data lines Support BC1.2 D+/D− handshake and QC2.0/QC3.0 voltage negotiation; must be shorted for BC1.2 compliance.
DISCH Fast Vbus discharge sink Internal low-RON switch discharges output to <0.8 V within USB-PD vSafe0V timing; includes millisecond-gated voltage check.
SW NMOS gate driver Charge-pump boosted (VCC + 6 V) output directly drives external NMOS load switch; ensures safe Vbus enable/disable sequencing.
GND Power ground Main ground reference for digital core, protections, and internal regulators; separate from SGND for noise isolation.
EDP Exposed die pad Thermal path to PCB copper; must be soldered to thermal pad for OTP derating and continuous 5 A operation.

Key Features

Feature Design Value
Dual-loop CV/CC regulation Independent 12-bit DAC (voltage) and 10-bit DAC (current) with continuous ADC measurement and <2 % full-scale accuracy.
Hardware safety co-processor All critical protections (OTP, OVP, OSP, OCP) implemented in analog/hardware logic - fully operational without MCU intervention.
Programmable PPS support Up to 4 of 7 MTP-stored PDOs configurable as PPS profiles (20 mV/step, 10 mA/step) for USB-PD 3.0 adaptive charging.
Adaptive cable compensation MTP-set compensation (0–200 mV/A) applied per PDO to offset IR drop; improves terminal voltage accuracy under load.
Integrated temperature sensing Two GPIO pins support NTC-based adapter/cable connector temperature monitoring with <5 °C accuracy (0–120 °C).
Single-optocoupler feedback Eliminates need for secondary-side shunt regulator; OPTO pin replaces TL431 cathode, reducing BOM count and layout complexity.

Applications

Smartphone Fast Charging Adapter USB-C Tablet Power Supply

Use Scenario: Compact wall charger delivering 45 W PPS output to flagship smartphones with dynamic voltage/current adjustment.

IC Role / Device Role / Timing Role: Secondary-side USB-PD 3.0 controller managing Vbus regulation, PPS negotiation, thermal foldback, and safe discharge via DISCH/SW pins.

Use Value: Enables CoC Tier-2 compliant <30 mW no-load power and hardware-enforced OTP/OVP, eliminating firmware-dependent safety risks.

Use Scenario: Multi-PDO USB-C power supply supporting 20 V/3 A fixed profile and 15 V/3 A PPS for tablet battery conditioning.

IC Role / Device Role / Timing Role: Protocol-aware SMPS supervisor coordinating TEA193x primary and TEA199x SR controllers via optocoupler feedback and I²C telemetry.

Use Value: Delivers 2% CV/CC accuracy across 2.9–21 V range using factory-trimmed DACs and MTP-compensated cable loss correction.

QC4+-Enabled Laptop Dock Charger Multi-Protocol Industrial USB Hub PSU

Use Scenario: 65 W laptop dock charger supporting QC4+, USB-PD, and BC1.2 for mixed-device environments.

IC Role / Device Role / Timing Role: Unified protocol engine handling DP/DM (QC), CC1/CC2 (PD), and D+/D− (BC1.2) handshakes with automatic fallback sequencing.

Use Value: Reduces design risk via hardware-detached vSafe5V enforcement and MTP-disabled QC during USB-PD certification testing.

Use Scenario: DIN-rail mounted USB hub power module requiring robust overtemperature and short-circuit protection in industrial settings.

IC Role / Device Role / Timing Role: Fail-safe secondary controller with dual external OTP inputs (GPIO1/GPIO2), open-ground detection, and latched fault shutdown.

Use Value: Guarantees safe shutdown below 50 mW dissipation during output short, meeting IEC 62368-1 touch-temperature and fire-risk requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar USB-PD secondary-side controller applications.

Alternative Part Technical Difference Application Difference Selection Advice
STUSB4500QTR Standalone USB-PD 3.0 sink controller; lacks integrated CV/CC SMPS regulation, NMOS gate drive (SW), and DISCH functionality. Requires external op-amp, MOSFET driver, and discharge circuit; not a drop-in replacement for SMPS feedback loop integration. Select when only PD communication is needed alongside discrete power stage control.
MPQ4282-AEC1 Automotive-grade USB-PD 3.0 controller with integrated buck converter; includes SW/DISCH but no GPIO-based NTC support or MTP-configurable PDO count. Fixed 3-PDO limit vs. TEA19051BAMTK/1J's 7-PDO (4 PPS) capability; rated for AEC-Q100 Grade 1, not optimized for consumer no-load power. Select for automotive infotainment power delivery where AEC-Q100 qualification and integrated buck are mandatory.

Compared with STUSB4500QTR and MPQ4282-AEC1, the TEA19051BAMTK/1J uniquely combines full SMPS secondary regulation (CV/CC), hardware safety co-processing, 7-PDO programmability, and dual NTC temperature sensing in a single HVSON16 package - enabling certified, compact, and thermally robust USB-C chargers with minimal external components.

Availability

TEA19051BAMTK/1J is available at Aetrix Electronics and suitable for USB-C fast-charging adapters, multi-protocol laptop docks, and industrial USB hub power supplies requiring stable component supply, long-term lifecycle support, and compliance with USB-PD 3.0, QC4+, and energy efficiency standards.

Supply support for TEA19051BAMTK/1J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and consumer applications, with deep expertise in power management and USB protocol IP.

The TEA19051BAMTK/1J belongs to NXP's TEA190xx smart-charging controller family, designed specifically for high-efficiency, safety-certified USB-C and Quick Charge power adapters targeting smartphone, tablet, and laptop markets.

FAQ

What protocols does the TEA19051BAMTK/1J support out of the box?

The TEA19051BAMTK/1J natively supports USB-PD 2.0 and 3.0 (including PPS), Qualcomm Quick Charge 2.0/3.0/4+, Battery Charging 1.2, and unstructured VDMs for vendor ID discovery. All protocol stacks execute on its embedded MCU, with MTP memory storing up to seven programmable power data objects (PDOs), four of which can be configured as PPS profiles. The TEA19051BAMTK/1J also includes hardware-level CC1/CC2 and DP/DM interfaces to ensure physical-layer compliance without firmware dependency.

How does the TEA19051BAMTK/1J achieve <30 mW no-load power consumption?

The TEA19051BAMTK/1J achieves sub-30 mW system-level no-load power through ultra-low-quiescent-current circuitry, intelligent peripheral gating during detach state, and hardware-managed power-down sequencing. When unattached, only essential blocks (CC detection, UVLO monitor, and 1 mA DISCH sink) remain active; analog loops and protocol engines shut down. Its HVSON16 package and optimized internal regulators minimize leakage, and the single-optocoupler feedback eliminates auxiliary bias supplies - all contributing to CoC Tier-2 and EuP Lot6 compliance. This performance is validated in reference designs combining TEA19051BAMTK/1J with TEA193x and TEA199x controllers.

Can the TEA19051BAMTK/1J replace a TL431 in existing SMPS designs?

Yes - the TEA19051BAMTK/1J is explicitly architected as a programmable, enhanced replacement for the TL431 shunt regulator. Its VSNS pin maps to TL431's REF input, OPTO pin to its cathode, and GND to its anode. Unlike the TL431, the TEA19051BAMTK/1J adds constant-current regulation, USB-PD/QC protocol handling, hardware protections, and MTP configurability - all while retaining pin-compatible feedback topology. Migration requires updating the resistor divider (per MTP-programmed ratio) and adding minimal support components (e.g., DISCH resistor, NTCs), but preserves the core optocoupler-based isolation scheme.

What thermal management features does the TEA19051BAMTK/1J provide?

The TEA19051BAMTK/1J provides three-tier thermal management: (1) internal die temperature monitoring via on-die sensor, (2) two configurable GPIO pins supporting NTC thermistors for adapter and cable-connector temperature measurement (<5 °C accuracy, 0–120 °C), and (3) hardware-latched OTP with user-defined thresholds stored in MTP. Both external NTC channels use adaptive current sources (15/60/240 µA) to maintain linearity across temperature ranges. The exposed die pad (EDP) serves as primary thermal path, requiring direct PCB copper connection for sustained >3 A operation and OTP derating control.

Is the TEA19051BAMTK/1J pin-compatible with other variants in the TEA19051B series?

Yes - all TEA19051Bx variants, including TEA19051BAMTK/1J, share identical HVSON16 (SOT1308-1) packaging and 100 % pin-to-pin compatibility. Differences between variants (e.g., TEA19051BAATK/1, TEA19051BABTK/1) reside solely in factory-programmed MTP contents - such as default PDO sets, cable compensation values, GPIO configurations, and protection thresholds - not in silicon or pin function. This allows design reuse across SKUs and field-upgradable feature sets via I²C or VDM-based MTP reprogramming.

TEA19051BAMTK/1J Specifications

Product attributes
Attribute value
Manufacturer:
NXP Semiconductors
Package/Case:
-
Programmable:
Not Verified
Protocol:
-
Function:
-
Interface:
-
Standards:
-
Voltage - Supply:
-
Current - Supply:
-
Operating Temperature:
-
Supplier Device Package:
-
Grade:
-
Qualification:
-

TEA19051BAMTK/1J FAQ

1.How can I place an order for TEA19051BAMTK/1J through Aetrix?

Please submit a Request for Quotation (RFQ) for TEA19051BAMTK/1J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TEA19051BAMTK/1J reliable?

The price and inventory of TEA19051BAMTK/1J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TEA19051BAMTK/1J is usually 5 days.

3.What payment methods are accepted for TEA19051BAMTK/1J?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TEA19051BAMTK/1J transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TEA19051BAMTK/1J?

TEA19051BAMTK/1J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TEA19051BAMTK/1J order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TEA19051BAMTK/1J?

For technical support, including TEA19051BAMTK/1J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TEA19051BAMTK/1J requirements.

6.How does Aetrix verify that TEA19051BAMTK/1J is sourced from the original manufacturer or authorized distributors?

All TEA19051BAMTK/1J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TEA19051BAMTK/1J meets industry standards.

7.What is the process for return or replacement of TEA19051BAMTK/1J?

All TEA19051BAMTK/1J units undergo pre-shipment inspection (PSI). If there is an issue with TEA19051BAMTK/1J, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TEA19051BAMTK/1J part is unused and in its original packaging.

Return procedure for TEA19051BAMTK/1J:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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