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NXP Semiconductors TEA19051BARTK/1J
- Part No.:
- TEA19051BARTK/1J
- Manufacturer:
- NXP Semiconductors
- Category:
- Controllers
- Package:
- -
- Datasheet:
-
TEA19051BARTK/1J.pdf
- Description:
- SMARTCHARG PROTOC CONTR QC4
- Quantity:
- Payment:
- Shipping:
Inventory:20,000
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Product details
Overview
TEA19051BARTK/1J from NXP Semiconductors is a secondary-side USB-PD 3.0 and QC4+ programmable controller for AC-DC SMPS, supporting CV/CC regulation with ±2 % output voltage and current accuracy, 2.9 V–21 V output range, and <30 mW no-load power in combination with TEA193x primary and TEA199x SR controllers.
For engineers reviewing the TEA19051BARTK/1J datasheet, TEA19051BARTK/1J pinout, TEA19051BARTK/1J application, or TEA19051BARTK/1J equivalent, key selection considerations include USB-PD 3.0 PPS support, hardware-enforced protections (OTP/OVP/OCP/OSP), integrated NMOS gate drive (SW pin), fast discharge (DISCH pin), and MTP-programmable PDOs and cable compensation.
Technical Context
The TEA19051BARTK/1J implements dual-loop regulation using an internal 12-bit DAC for voltage control (VSNS) and 10-bit DAC for current control (ISNS), with continuous ADC-based measurement and hardware-accelerated USB-PD PHY for CC1/CC2 communication. Its digital core includes embedded ROM/RAM/MTP memory and adaptive current sources for NTC-based temperature sensing on GPIO1/GPIO2.
Protection architecture is fully hardware-based-OTP (internal + two external), adaptive OVP/UVP, OSP, OSUP, OGP, and soft-short detection on CC1/CC2 and output-all configurable as latched or safe-restart via MTP. The SW pin drives an external NMOS load switch using an integrated charge pump (VCC + 6 V), while DISCH provides controlled Vbus discharge with real-time vSafe0V verification.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage Range | 2.9 V to 21 V; supports USB-PD PPS and QC4+ variable profiles with programmable PDOs |
| CV/CC Accuracy | Better than ±2 % at full load; enables tight regulation for USB-C PD compliance and smartphone fast charging |
| No-Load Power | <30 mW system-level; achieved via ultra-low-power circuitry and intelligent sleep mode during unattached state |
| Protocol Support | USB-PD 2.0/3.0 (including PPS), QC2.0/QC3.0/QC4+, BC1.2, USB Type-C v1.3; all implemented in hardware/firmware |
| Protection Architecture | Fully hardware-enforced OTP/OVP/UVP/OCP/OSP/OSUP/OGP; independent of MCU operation for fail-safe behavior |
| Package & Pin Count | HVSON16 (SOT1308-1); 3.5 × 5.5 × 0.85 mm body; 16-pin layout optimized for compact USB-C adapter designs |
| MTP Memory | Non-volatile multi-time programmable memory storing PDOs, cable compensation, GPIO functions, and protection thresholds |
Pinout & Package
HVSON16 package (SOT1308-1), 3.5 × 5.5 × 0.85 mm body, leadless, reflow-solder compatible, with exposed die pad (EDP) for thermal dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Supply input | Secondary-side DC supply rail (up to 21 V); powers internal circuits and triggers UVLO below ≈3 V |
| OPTO | Optocoupler driver output | Replaces TL431 cathode; drives optocoupler LED to regulate primary-side controller via feedback loop |
| SGND | Sense ground reference | Isolated ground return for ISNS and VSNS to avoid noise coupling into precision analog loops |
| GPIO1 / GPIO2 | Configurable I/O | Support NTC thermistor interface (adapter/cable temp), OTP, or auxiliary supply; adaptive current sourcing ensures ±5 °C accuracy |
| ISNS | Current sense input | Accepts mΩ-shunt voltage (×50 gain); enables CC-mode regulation and OCP with 0.3 A–5 A programmable range |
| VSNS | Voltage sense input | Resistive divider input for CV-mode; matches MTP-programmed ratio (e.g., 1/8.325 for ≤20 V PDOs) |
| SCL / SDA | I²C interface | Used for VDM-based configuration (VID/PID), temperature readback, and MTP programming during development |
| DM / DP | QC/Battery Charging interface | Supports QC2.0/QC3.0 handshake and BC1.2 D+/D− detection; must be shorted for BC1.2 compliance |
| CC1 / CC2 | USB-C CC line interface | Hardware-based attach/detach detection and USB-PD 3.0 packet communication; supports vSafe5V/vSafe0V transitions |
| DISCH | Fast discharge sink | Internal low-RON switch + external resistor discharges Vbus to <0.8 V within USB-PD hard-reset timing |
| GND | Power ground | Main system ground reference; separate from SGND to maintain signal integrity in high-accuracy sensing |
| SW | NMOS gate driver | Charge-pump boosted output (VCC + 6 V) directly drives external NMOS load switch; ensures safe Vbus isolation |
| EDP | Exposed die pad | Thermally connected to die; must be soldered to PCB copper for effective heat dissipation in high-power adapters |
Key Features
| Feature | Design Value |
|---|---|
| Dual-loop CV/CC regulation | 12-bit voltage DAC + 10-bit current DAC enable precise, independent control of output parameters per PDO |
| Hardware-enforced safety | All critical protections (OTP/OVP/OCP/OSP) implemented in analog/hardware logic-functional even if MCU locks up |
| Programmable PPS support | Up to 4 of 7 PDOs configurable as PPS; enables 20 mV/step voltage and 50 mA/step current adjustments for USB-PD 3.0 |
| Integrated thermal monitoring | Two GPIO pins support NTC-based temperature sensing (cable + adapter) with hardware OTP trigger and ±5 °C accuracy |
| Ultra-low standby consumption | <30 mW system no-load power achieved via dynamic circuit gating and minimal active peripherals during unattached state |
| Single-optocoupler architecture | Eliminates need for secondary-side shunt regulator; reduces BOM count to ~15 components and improves reliability |
Applications
| Smartphone Fast Charging Adapter | Multi-Protocol Laptop Charger |
|---|---|
Use Scenario: Compact 45 W USB-C wall charger delivering QC4+ and USB-PD 3.0 PPS to flagship smartphones with dynamic voltage/current negotiation. IC Role / Device Role / Timing Role: Secondary-side protocol controller managing Vbus regulation, load switching, discharge, and thermal safety via SW/DISCH/CC1/CC2/GPIO pins. Use Value: Enables single-chip compliance with USB-PD 3.0, QC4+, and BC1.2-reducing design complexity and certification effort versus discrete protocol IC + MCU solutions. | Use Scenario: 65 W GaN-based laptop adapter supporting simultaneous USB-PD PPS (for battery charging) and legacy QC3.0 (for accessories). IC Role / Device Role / Timing Role: Central SMPS controller coordinating primary-side TEA193x and SR TEA199x, executing real-time PDO negotiation and cable compensation. Use Value: Hardware-accelerated USB-PD PHY and MTP-stored 7-PDO table allow seamless multi-device compatibility without firmware updates. |
| USB-C Power Bank Output Stage | Universal Travel Adapter |
Use Scenario: Bidirectional power bank with USB-C input/output, requiring precise CC/CV control and overtemperature shutdown during high-current discharge. IC Role / Device Role / Timing Role: Secondary-side regulator enforcing current limits and thermal derating via ISNS and GPIO2 NTC monitoring. Use Value: Integrated 2 % CC accuracy and hardware OTP eliminate need for external current-sense amplifier and discrete thermal IC-saving board space and cost. | Use Scenario: Dual-input (USB-A + USB-C) travel adapter supporting global voltage inputs and dynamically selecting optimal protocol per connected device. IC Role / Device Role / Timing Role: Protocol arbiter detecting plug type (CC vs DP/DM), enabling appropriate stack (USB-PD vs QC), and configuring PDOs via MTP. Use Value: Single IC replaces multiple protocol-specific controllers; MTP programmability allows region- or OEM-specific PDO tuning without hardware change. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar USB-PD and QC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STUSB4500QTR | Standalone USB-PD 3.0 sink controller; lacks QC support, CC/CV DACs, and integrated SW/DISCH drivers | Requires external MCU for QC protocols and separate load switch/discharge circuitry | Choose when only USB-PD 3.0 compliance is needed and system already includes QC-capable MCU |
| MPQ4282GQ-AEC1 | Automotive-grade USB-PD 3.0 controller with AEC-Q100 qualification; no QC support; different pinout and MTP structure | Targeted for vehicle-mounted chargers; higher operating temperature range but no smartphone QC ecosystem integration | Prefer for automotive infotainment or telematics power supplies where AEC-Q100 is mandatory |
Compared with STUSB4500QTR and MPQ4282GQ-AEC1, the TEA19051BARTK/1J uniquely integrates QC4+ protocol handling, hardware-based dual-loop regulation, and direct NMOS/SW drive-enabling complete secondary-side control in consumer-grade USB-C adapters with minimal external components.
Availability
TEA19051BARTK/1J is available at Aetrix Electronics and suitable for USB-C fast charging adapters, multi-protocol laptop power supplies, and universal travel chargers requiring stable component supply, long-term lifecycle support, and certified USB-PD 3.0/PPS functionality.
Supply support for TEA19051BARTK/1J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and consumer applications, with leadership in USB-PD, wireless charging, and high-efficiency power management ICs.
The TEA19051BARTK/1J belongs to NXP's TEA190xx family of smart-charging controllers, designed specifically for compact, high-efficiency USB-C SMPS implementations targeting CoC Tier-2, EuP Lot 6, and DOE Level VI efficiency standards.
FAQ
What USB-PD and QC protocols does the TEA19051BARTK/1J support?
The TEA19051BARTK/1J supports USB-PD 2.0 and 3.0-including Programmable Power Supply (PPS)-as well as Qualcomm QuickCharge QC2.0, QC3.0, and QC4+. It also complies with USB Type-C v1.3 and Battery Charging 1.2 (BC1.2). Protocol selection is managed via MTP configuration, and QC2.0/QC3.0 can be disabled to pass USB-PD certification testing. The TEA19051BARTK/1J implements all protocol layers in dedicated hardware blocks for deterministic timing and robustness.
How does the TEA19051BARTK/1J achieve <30 mW no-load power?
The TEA19051BARTK/1J achieves <30 mW system-level no-load power through aggressive power gating of non-essential circuits during unattached state, ultra-low-quiescent-current biasing, and hardware-controlled sleep modes that retain MTP settings and GPIO configurations. Its HVSON16 package and optimized internal regulators minimize leakage, while the DISCH pin's 1 mA sink (active only when switches are off) prevents unintended Vbus hold-up. This performance meets CoC Tier-2 and DOE Level VI requirements when paired with TEA193x/TEA199x controllers.
What is the role of the SW and DISCH pins on the TEA19051BARTK/1J?
The SW pin is a charge-pump boosted (VCC + 6 V) NMOS gate driver that directly controls an external load switch between VCC and Vbus, ensuring safe isolation during faults. The DISCH pin contains an internal low-RON switch used with an external resistor to rapidly discharge Vbus to <0.8 V for USB-PD vSafe0V compliance. Both pins operate independently of the MCU core-SW remains low during UVLO, and DISCH performs periodic voltage sampling during hard reset to verify discharge completion. These functions are integral to the TEA19051BARTK/1J's fail-safe architecture.
Can the TEA19051BARTK/1J be used without an optocoupler?
No-the TEA19051BARTK/1J requires an optocoupler connected between the OPTO pin and the primary-side controller's feedback node to close the regulation loop. The OPTO pin functions as a TL431 cathode replacement, sinking current to adjust primary-side duty cycle. While the TEA19051BARTK/1J integrates all secondary-side sensing, protocol, and protection functions, galvanic isolation mandates the optocoupler for safety-compliant AC-DC designs. Removing it disables CV/CC regulation and violates regulatory requirements for Class II power supplies.
How many power data objects (PDOs) can be programmed into the TEA19051BARTK/1J?
The TEA19051BARTK/1J supports up to seven programmable power data objects (PDOs) stored in its non-volatile MTP memory. Four of these can be configured as Programmable Power Supply (PPS) PDOs, while the remaining three are Fixed PDOs. Each PDO includes independently configurable voltage, current, and flags (e.g., unchunked, USB communications capable). Default PDO sets are factory-programmed per variant (e.g., TEA19051BARTK/1J), and custom PDOs can be written via I²C using vendor-defined messages (VDMs) during production or field update.
TEA19051BARTK/1J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- -
- Programmable:
- Not Verified
- Protocol:
- -
- Function:
- -
- Interface:
- -
- Standards:
- -
- Voltage - Supply:
- -
- Current - Supply:
- -
- Operating Temperature:
- -
- Supplier Device Package:
- -
- Grade:
- -
- Qualification:
- -
TEA19051BARTK/1J FAQ
1.How can I place an order for TEA19051BARTK/1J through Aetrix?
Please submit a Request for Quotation (RFQ) for TEA19051BARTK/1J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TEA19051BARTK/1J reliable?
The price and inventory of TEA19051BARTK/1J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TEA19051BARTK/1J is usually 5 days.
3.What payment methods are accepted for TEA19051BARTK/1J?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TEA19051BARTK/1J transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TEA19051BARTK/1J?
TEA19051BARTK/1J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TEA19051BARTK/1J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TEA19051BARTK/1J?
For technical support, including TEA19051BARTK/1J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TEA19051BARTK/1J requirements.
6.How does Aetrix verify that TEA19051BARTK/1J is sourced from the original manufacturer or authorized distributors?
All TEA19051BARTK/1J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TEA19051BARTK/1J meets industry standards.
7.What is the process for return or replacement of TEA19051BARTK/1J?
All TEA19051BARTK/1J units undergo pre-shipment inspection (PSI). If there is an issue with TEA19051BARTK/1J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TEA19051BARTK/1J part is unused and in its original packaging.
Return procedure for TEA19051BARTK/1J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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