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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > PFC (Power Factor Correction)

NXP Semiconductors TEA19162HT/2J

Name: TEA19162HT/2J
Brand: NXP Semiconductors
SKU: TEA19162HT/2J
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: TEA19162HT/2J

Manufacturer:: NXP Semiconductors

Category:: PFC (Power Factor Correction)

Package:: 8-SOIC (0.154", 3.90mm Width)

Datasheet:: TEA19162HT/2J.pdf

Description:: IC PFC CONTROLLER SO8

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Product details

Overview

TEA19162HT/2J from NXP Semiconductors is a dedicated Power Factor Correction (PFC) controller IC for resonant power supplies, operating in quasi-resonant and discontinuous conduction modes with valley switching. It delivers accurate boost voltage regulation (±1.5% at 2.5 V reference), supports universal AC input (70–276 V_AC), enables active X-capacitor discharge without external components, and targets 90–500 W systems used in desktop PCs and LCD TVs.

For engineers reviewing the TEA19162HT/2J datasheet, TEA19162HT/2J pinout, TEA19162HT/2J application, or TEA19162HT/2J equivalent, key selection considerations include its integrated mains compensation for Class-D harmonic compliance, fast latch reset for reliable fault recovery, burst-mode coordination with TEA19161T, 8-pin SO8 package, and dual protection signaling via SNSBOOST pin.

Technical Context

The TEA19162HT/2J implements ton-controlled PFC regulation using an internal transconductance error amplifier referenced to a trimmed 2.63 V on SNSBOOST, with dynamic gm adjustment during transients to prevent false OVP triggering. Its valley detection logic uses SNSAUX to synchronize MOSFET turn-on after demagnetization, minimizing switching losses and EMI.

Protections are tightly coupled with the TEA19161T LLC controller via shared SUPIC and SNSBOOST pins: OVP, SCP, OLP, OTP, and brownin/brownout are enforced through coordinated voltage thresholds (e.g., Vovp(stop) = 2.63 V, Vscp(stop) = 0.4 V) and latched or soft-stop responses, while fast latch reset activates upon mains reconnection to avoid long SUPIC discharge delays.

Key Specifications

Parameter	Value and Actual Design Meaning
Topology Support	Quasi-resonant and discontinuous conduction mode PFC with valley switching - enables zero-voltage turn-on for reduced EMI and conduction loss.
Input Voltage Range	70 V_AC to 276 V_AC - enables single-design global mains compatibility without hardware change.
Boost Regulation Accuracy	±1.5% at 2.5 V reference - ensures stable 385 V DC bus under line/load variation for downstream LLC stage.
Active X-Cap Discharge	Integrated circuitry discharges X-capacitors post-mains removal - eliminates need for external bleed resistors and meets IEC 62368-1 touch-current safety limits.
Supply Current (Burst)	200 µA - minimizes no-load system power to <75 mW when paired with TEA19161T/TEA1995T.
Protection Signaling	SNSBOOST pin used for bidirectional PFC-LLC fault coordination - supports soft stop (2.8–3.23 V window), OVP (2.63 V), and fast latch reset (2.0 V pulse).
Mains Compensation	Real-time current-based sensing on SNSMAINS pin - maintains constant loop bandwidth across full AC range for Class-D harmonic compliance.

Pinout & Package

TEA19162HT/2J is housed in an 8-lead plastic small outline package (SO8, body width 3.9 mm, SOT96-1), optimized for high-voltage PFC board layout with GND-isolated sense and gate drive paths.

Pin/Terminal	Circuit Role	Design Meaning
GATEPFC (Pin 1)	PFC MOSFET gate driver output	Drives external high-voltage MOSFET with controlled slew rate; supports active X-cap discharge via slow charge/discharge current sources.
GND (Pin 2)	Power and signal ground reference	Common return for all analog and digital blocks; requires low-inductance PCB connection to minimize noise coupling into SNSCUR/SNSAUX.
SNSCUR (Pin 3)	Cycle-by-cycle current sense input	Monitors source current of PFC MOSFET via external Rsense; triggers OCP when voltage exceeds 0.5 V threshold.
SUPIC (Pin 4)	IC supply voltage input	Accepts 9–22 V DC; initiates start-up at 13 V typical; includes UVP (9 V) and hysteresis (0.7 V) for robust brownout recovery.
SNSBOOST (Pin 5)	Boost output voltage feedback	Inputs scaled PFC bus voltage; sets 2.63 V OVP threshold and enables burst-mode coordination with TEA19161T via 2.8–3.23 V window.
SNSMAINS (Pin 6)	Mains voltage and external OTP sensing	Measures peak mains current for brownin/brownout (Ibi/Ibo) and sources current for NTC-based external temperature monitoring.
PFCCOMP (Pin 7)	Frequency compensation network node	Connects external RC network to set loop bandwidth; clamped at 3.8 V max; ton control range defined between 1.23 V (max on-time) and 3.5 V (zero on-time).
SNSAUX (Pin 8)	Auxiliary winding input for demag/valley detection	Detects transformer demagnetization and MOSFET drain-source valley; includes internal 44.5 µs demag timeout and 3.8 µs valley timeout fallbacks.

Key Features

Feature	Design Value
Valley/zero-voltage switching	Reduces switching losses and EMI by ensuring MOSFET turn-on only at minimum drain-source voltage, validated via SNSAUX timing.
Integrated X-capacitor discharge	Eliminates external bleed resistors by using GATEPFC to actively discharge X-caps post-mains removal, meeting IEC 62368-1 safety requirements.
Universal AC input operation	Supports 70–276 V_AC without configuration change, enabled by adaptive mains compensation on SNSMAINS and wide SUPIC voltage range.
Fast latch reset mechanism	Releases latched protections (e.g., OTP, OVP) within milliseconds of mains reconnection-no need to fully discharge bulk capacitors or cycle power.
Burst-mode coordination with TEA19161T	Enables system-level efficiency optimization below 20% load by synchronizing PFC shutdown/startup via SNSBOOST voltage window (2.8–3.23 V).

Applications

Desktop PC Power Supplies	LCD Television Power Stages
Use Scenario: 250–400 W ATX-compliant power supply delivering +12 V, +5 V, and +3.3 V rails with Energy Star 80 PLUS Gold efficiency. IC Role / Device Role / Timing Role: Primary-side PFC controller regulating boost stage to generate stable 385 V DC bus; coordinates with TEA19161T LLC for seamless burst-mode transition at light load. Use Value: Achieves <75 mW no-load input power and >92% peak efficiency across 20–100% load, satisfying DoE Level VI and EU Eco-design requirements.	Use Scenario: Slim-panel LCD TV power supply with integrated PFC+LLC architecture, requiring compact board area and low acoustic noise. IC Role / Device Role / Timing Role: PFC controller implementing valley-switched DCM to suppress audible transformer whine during soft-start and light-load burst mode. Use Value: Enables silent operation via controlled GATEPFC slew rate and soft-stop OVP response, eliminating mechanical vibration in thin-form-factor enclosures.
Notebook Adapter Systems	Gaming Console Power Units
Use Scenario: 120–180 W GaN-based notebook adapter targeting USB PD 3.1 programmable power supply compliance. IC Role / Device Role / Timing Role: High-accuracy PFC stage providing tightly regulated 385 V bus for downstream GaN LLC; uses SNSMAINS for real-time mains compensation to meet IEC 61000-3-2 Class D. Use Value: Maintains THD <8% across 90–264 V_AC input, enabling single-BOM global deployment without derating or filter redesign.	Use Scenario: 350–450 W gaming console PSU requiring high reliability, thermal resilience, and rapid fault recovery during intense GPU load cycles. IC Role / Device Role / Timing Role: PFC controller with dual OTP (internal + external NTC on SNSMAINS) and fast latch reset to survive repeated thermal stress events without manual intervention. Use Value: Reduces field failure rate by enabling automatic recovery from overtemperature faults within 100 ms of cooling, avoiding forced system shutdowns.

Desktop PC Power Supplies

LCD Television Power Stages

Use Scenario: 250–400 W ATX-compliant power supply delivering +12 V, +5 V, and +3.3 V rails with Energy Star 80 PLUS Gold efficiency.

IC Role / Device Role / Timing Role: Primary-side PFC controller regulating boost stage to generate stable 385 V DC bus; coordinates with TEA19161T LLC for seamless burst-mode transition at light load.

Use Value: Achieves <75 mW no-load input power and >92% peak efficiency across 20–100% load, satisfying DoE Level VI and EU Eco-design requirements.

Use Scenario: Slim-panel LCD TV power supply with integrated PFC+LLC architecture, requiring compact board area and low acoustic noise.

IC Role / Device Role / Timing Role: PFC controller implementing valley-switched DCM to suppress audible transformer whine during soft-start and light-load burst mode.

Use Value: Enables silent operation via controlled GATEPFC slew rate and soft-stop OVP response, eliminating mechanical vibration in thin-form-factor enclosures.

Notebook Adapter Systems

Gaming Console Power Units

Use Scenario: 120–180 W GaN-based notebook adapter targeting USB PD 3.1 programmable power supply compliance.

IC Role / Device Role / Timing Role: High-accuracy PFC stage providing tightly regulated 385 V bus for downstream GaN LLC; uses SNSMAINS for real-time mains compensation to meet IEC 61000-3-2 Class D.

Use Value: Maintains THD <8% across 90–264 V_AC input, enabling single-BOM global deployment without derating or filter redesign.

Use Scenario: 350–450 W gaming console PSU requiring high reliability, thermal resilience, and rapid fault recovery during intense GPU load cycles.

IC Role / Device Role / Timing Role: PFC controller with dual OTP (internal + external NTC on SNSMAINS) and fast latch reset to survive repeated thermal stress events without manual intervention.

Use Value: Reduces field failure rate by enabling automatic recovery from overtemperature faults within 100 ms of cooling, avoiding forced system shutdowns.

Equivalent & Alternatives

The following parts are listed as comparable options for similar PFC controller applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
UCC28070DR	Fixed-frequency continuous conduction mode (CCM); no valley switching or active X-cap discharge; requires external OVP comparator.	Targeted at higher-power (>500 W), lower-cost industrial SMPS where EMI filtering budget allows CCM operation.	Select UCC28070DR only if CCM topology, cost sensitivity, and absence of active X-cap discharge are acceptable trade-offs.
FAN9612IN	Transitional-mode (TM) PFC with proprietary valley detection; lacks integrated mains compensation and burst-mode signaling interface for LLC coordination.	Suitable for standalone PFC stages feeding conventional PWM converters-not optimized for resonant PFC+LLC combos.	Choose FAN9612IN when designing non-synchronized PFC-only supplies without need for TEA19161T interoperability.

Compared with UCC28070DR and FAN9612IN, TEA19162HT/2J uniquely integrates valley-switched QR/DCM operation, active X-cap discharge, and bidirectional SNSBOOST-based communication with TEA19161T-enabling ultra-low no-load power, Class-D compliance across universal input, and seamless burst-mode handoff in resonant topologies.

Availability

TEA19162HT/2J is available at Aetrix Electronics and suitable for desktop PC power supplies, LCD television main boards, and gaming console power units requiring stable component supply, long-term lifecycle support, and compliance with Energy Star, DoE Level VI, and EU Eco-design directives.

Supply support for TEA19162HT/2J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a Dutch semiconductor company specializing in secure connectivity solutions, automotive processors, and high-efficiency power management ICs for consumer, industrial, and automotive markets.

The TEA19162HT/2J belongs to NXP's TEA19xx resonant power supply controller family, designed specifically for high-efficiency, low-noise, and safety-compliant AC-DC conversion in 90–500 W resonant PFC+LLC architectures.

FAQ

What is the primary function of the TEA19162HT/2J in a power supply design?

The TEA19162HT/2J is a dedicated Power Factor Correction (PFC) controller IC that regulates the boost stage in resonant AC-DC power supplies. It ensures high power factor (>0.95), low THD, and stable 385 V DC bus generation across universal AC input (70–276 V_AC), while coordinating with the TEA19161T LLC controller via shared SNSBOOST signaling. Its valley-switched operation directly enables the efficiency and EMI performance required in modern 80 PLUS Gold/Platinum designs.

How does the TEA19162HT/2J achieve ultra-low no-load power consumption?

The TEA19162HT/2J achieves <75 mW total system no-load power by combining multiple low-power design features: 200 µA supply current in burst mode, integrated active X-capacitor discharge eliminating bleed resistors, soft-start/soft-stop transitions that avoid inrush currents, and precise coordination with TEA19161T to disable the PFC stage entirely during light-load conditions. This behavior is validated in reference designs meeting Energy Star and DoE Level VI standby power requirements.

Can the TEA19162HT/2J be used without the TEA19161T LLC controller?

Yes, the TEA19162HT/2J can operate as a standalone PFC controller, but several key features-including burst-mode coordination, fast latch reset signaling, and synchronized soft-start sequencing-are optimized for use with the TEA19161T. When used alone, designers must implement external circuitry for OVP, brownout detection, and X-cap discharge, and cannot leverage the SNSBOOST-based protection handshake. The datasheet confirms functional independence but highlights synergy in combo mode.

What protection mechanisms are implemented on the SNSBOOST pin of the TEA19162HT/2J?

The SNSBOOST pin of the TEA19162HT/2J implements four distinct protection functions: Soft Stop OVP (2.8–3.23 V window), Hard OVP (2.63 V trip), Short-Circuit Protection (SCP at 0.4 V), and Open-Loop Protection (OLP, also triggered below 0.4 V). These thresholds are internally fixed and enable bidirectional fault signaling with the TEA19161T-e.g., pulling SNSBOOST below 0.4 V disables the PFC, while raising it into the 2.8–3.23 V window forces burst mode. All are validated in Section 8.3 of the official datasheet.

What is the role of the SNSMAINS pin in the TEA19162HT/2J, and how is it used for both brownin/brownout and external OTP?

The SNSMAINS pin serves a dual function: it measures peak mains current for brownin/brownout detection (Ibi/Ibo thresholds) and sources current for external NTC-based temperature monitoring. During normal operation, it sinks current proportional to mains voltage; when mains drops below brownout level, it switches to sourcing mode to read the NTC resistance. This integrated approach eliminates separate sensing circuits and is explicitly detailed in Section 8.3.2 of the TEA19162HT/2J datasheet, including timing constraints (e.g., tdet(NTC)max = 1 ms).

TEA19162HT/2J Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: GreenChip™

Package/Case:: 8-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Mode:: Discontinuous Conduction (DCM)

Frequency - Switching:: 134kHz

Current - Startup:: 800 µA

Voltage - Supply:: 70 ~ 276 VAC

Operating Temperature:: -40°C ~ 150°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-SO

TEA19162HT/2J FAQ

1.How can I place an order for TEA19162HT/2J through Aetrix?

Please submit a Request for Quotation (RFQ) for TEA19162HT/2J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TEA19162HT/2J reliable?

The price and inventory of TEA19162HT/2J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TEA19162HT/2J is usually 5 days.

3.What payment methods are accepted for TEA19162HT/2J?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TEA19162HT/2J transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TEA19162HT/2J?

TEA19162HT/2J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TEA19162HT/2J order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TEA19162HT/2J?

For technical support, including TEA19162HT/2J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TEA19162HT/2J requirements.

6.How does Aetrix verify that TEA19162HT/2J is sourced from the original manufacturer or authorized distributors?

All TEA19162HT/2J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TEA19162HT/2J meets industry standards.

7.What is the process for return or replacement of TEA19162HT/2J?

All TEA19162HT/2J units undergo pre-shipment inspection (PSI). If there is an issue with TEA19162HT/2J, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TEA19162HT/2J part is unused and in its original packaging.

Return procedure for TEA19162HT/2J:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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