Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Power Supply Controllers, Monitors

NXP Semiconductors TEA2017ABT/2Y

Name: TEA2017ABT/2Y
Brand: NXP Semiconductors
SKU: TEA2017ABT/2Y
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: TEA2017ABT/2Y

Manufacturer:: NXP Semiconductors

Category:: Power Supply Controllers, Monitors

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: TEA2017ABT/2Y.pdf

Description:: PFC + RESONANT POWER SUPPLY CONT

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,500

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

TEA2017ABT/2 from NXP Semiconductors is a digital configurable dual-mode controller integrating DCM/QR PFC and LLC resonant control in a single SO16 package. It delivers precise primary-capacitor-voltage-based output power regulation, supports three dynamic operating modes (high-power, low-power, burst), and enables <75 mW no-load input power in combination with TEA2095T for 90–500 W high-efficiency AC-DC supplies used in gaming PSUs and LCD TVs.

For engineers reviewing the TEA2017ABT/2 datasheet, TEA2017ABT/2 pinout, TEA2017ABT/2 application, or TEA2017ABT/2 equivalent, key selection considerations include its digitally programmable mode transition thresholds, integrated X-cap discharge, valley-detection-enabled ZVS, configurable OCP/OPP/OTP protection levels, and GUI-assisted tuning of soft-start, jitter, and audible-noise suppression.

Technical Context

The TEA2017ABT/2 implements a hardware-state-machine-based digital architecture for deterministic real-time control of both PFC and LLC stages. Its V_CAP-based regulation loop directly measures delivered output power to determine operating mode transitions-eliminating frequency-loop gain variation and enabling accurate, load-dependent burst/low-power entry points.

It integrates high-voltage start-up (via DRAINPFC), bootstrap-supplied high-side gate drivers (GATEHS/SUPHS), and dual-sensing paths: SNSCURLLC for resonant current and SNSCAP for primary capacitor voltage. Protection functions-including CMR, OVP, OPP, OTP, and ICP-are independently programmable via MTP memory with latched or auto-restart behavior.

Key Specifications

Parameter	Value and Actual Design Meaning
PFC Mode	Discontinuous Conduction Mode (DCM) / Quasi-Resonant (QR) - enables high PF & low THD without boost diode reverse recovery losses.
LLC Regulation Method	V_CAP-based primary capacitor voltage sensing - provides direct output power measurement for stable mode transitions and no-frequency-loop compensation.
No-Load Input Power	<75 mW (with TEA2095T) - eliminates need for auxiliary supply and meets Energy Star/EuP Eco-design requirements.
Operating Modes	Three programmable modes: high-power (continuous switching), low-power (3-half-cycle hold), burst (programmable T_burst) - optimized for efficiency across full 0–100% load range.
Protection Features	Configurable OCP, OPP, OTP, OVP, UVP, CMR, ICP, brown-in/out - each with independent trip level, timer, and latch/restart policy stored in MTP.
Start-up Supply	Integrated HV current source from DRAINPFC to SUPIC - enables self-starting from rectified mains without external bias winding during initial charge.
Package	SO16 (SOT109-1), 3.9 mm body width - surface-mount compatible with standard PCB assembly and thermal management for high-density PSU designs.

Pinout & Package

TEA2017ABT/2 is housed in a plastic small-outline package (SO16, SOT109-1) with 16 leads and 3.9 mm body width. The package supports standard reflow profiles and provides adequate creepage/clearance for 475 V_DC operation.

Pin/Terminal	Circuit Role	Design Meaning
SNSMAINS (1)	Mains voltage & external temperature sense	Enables brown-in/out detection and system-level thermal derating using single resistor divider.
SNSBOOST (2)	Boost voltage feedback	Monitors PFC output voltage for accurate regulation; threshold V_start(SNSBOOST) triggers LLC enable.
SNSCURPFC (3)	PFC current sense	Detects zero-current crossing and peak current for DCM/QR timing and OCP.
GND (4)	Signal ground reference	Common return for analog sensing and digital core; isolated from power ground per layout guidelines.
GATEPFC (5)	PFC MOSFET gate driver	Drives external PFC switch with programmable slew rate and dead-time control.
GATELS (6)	LLC low-side gate driver & bootstrap supply	Drives LLC low-side MOSFET and charges external CSUPHS capacitor for high-side drive.
DRAINPFC (8)	HV start-up source & X-cap discharge	Provides internal HV current for SUPIC charging, valley detection, and automatic X-cap discharge at shutdown.
GATEHS (9)	LLC high-side gate driver	Drives high-side MOSFET using floating SUPHS rail; synchronized with GATELS for ZVS assurance.
SUPHS (10)	High-side driver floating supply	Input for external bootstrap capacitor (CSUPHS); referenced to HB node for level-shifting.
HB (11)	Half-bridge node sense	Connects to LLC bridge midpoint for slope detection and valley/peak timing critical for ZVS.
SUPIC (13)	Main IC supply input	Powered initially by DRAINPFC HV source, then by LLC auxiliary winding; regulated to V_start(SUPIC) during burst/non-switching.
SNSCAP (14)	LLC primary capacitor voltage sense	Divided input for V_hs/V_ls(SNSCAP) thresholds - core signal for power-regulated mode control.
SNSCURLLC (15)	LLC resonant current sense	Measures primary current for OCP, CMR, and startup current limiting; referenced to GND.
SNSFB (16)	Output voltage feedback & power-good	Optocoupler input for secondary regulation; also outputs POWER_GOOD signal when V_OUT is stable.

Key Features

Feature	Design Value
Dual-controller integration	Single SO16 IC replaces discrete PFC + LLC controllers - reduces BOM count, layout area, and design cycle time.
Programmable mode transitions	Three operating modes (high-power/low-power/burst) with user-defined power thresholds - enables optimization for efficiency vs. audible noise trade-offs.
X-capacitor discharge	Internal discharge path via DRAINPFC - eliminates external bleed resistors and associated standby power loss.
Valley/zero-voltage switching	Hardware-accelerated valley detection on HB node - ensures ZVS across wide load range, minimizing switching losses.
GUI-based configuration	Real-time parameter tuning (soft-start, jitter, burst frequency) via NXP GUI - accelerates prototyping without firmware changes.
Secure configuration storage	MTP memory with read-protection - prevents cloning of proprietary power supply settings and IP.

Applications

Desktop & All-in-One PCs	Gaming Power Supplies
Use Scenario: High-efficiency 300–500 W ATX-compatible PSU with tight no-load power limits and transient response demands. IC Role / Device Role / Timing Role: Primary controller managing PFC stage and LLC half-bridge; regulates output via SNSCAP and enforces burst-mode entry below 5 W load. Use Value: Achieves <75 mW system no-load power and >92% efficiency at 50% load - compliant with 80 PLUS Titanium and EU Eco-design Tier 2.	Use Scenario: Modular 750 W PSU with dynamic load steps (0→100% in <1 ms) and acoustic noise constraints. IC Role / Device Role / Timing Role: Dual-stage controller coordinating PFC and LLC timing; uses low-power mode hold periods and burst-on delay to suppress audible coil whine during light loads. Use Value: Eliminates need for auxiliary supply while maintaining <20 dB(A) acoustic noise at 23°C ambient - validated per SPECpower SSJ2008.
LCD Television	Notebook Adapters
Use Scenario: Slim 200 W open-frame PSU for 55″ 4K TV with EMI-sensitive display interface and thermal-limited enclosure. IC Role / Device Role / Timing Role: Digital PFC+LLC controller implementing PFC jitter and burst-mode frequency programming to shift EMI peaks outside critical bands. Use Value: Reduces conducted EMI by 8 dBμV at 150 kHz–30 MHz without added filtering - passes CISPR-32 Class B with 3 dB margin.	Use Scenario: 90 W GaN-based notebook adapter requiring ultra-low standby power and fast transient recovery. IC Role / Device Role / Timing Role: Combo controller regulating PFC output and LLC primary capacitor; uses SNSFB current regulation to maintain 100 μA opto-current during burst mode. Use Value: Enables 0.03 W no-load consumption and <100 μs recovery from 20%→100% load step - exceeds DOE Level VI and EU CoC v5 Tier 2.

Desktop & All-in-One PCs

Gaming Power Supplies

Use Scenario: High-efficiency 300–500 W ATX-compatible PSU with tight no-load power limits and transient response demands.

IC Role / Device Role / Timing Role: Primary controller managing PFC stage and LLC half-bridge; regulates output via SNSCAP and enforces burst-mode entry below 5 W load.

Use Value: Achieves <75 mW system no-load power and >92% efficiency at 50% load - compliant with 80 PLUS Titanium and EU Eco-design Tier 2.

Use Scenario: Modular 750 W PSU with dynamic load steps (0→100% in <1 ms) and acoustic noise constraints.

IC Role / Device Role / Timing Role: Dual-stage controller coordinating PFC and LLC timing; uses low-power mode hold periods and burst-on delay to suppress audible coil whine during light loads.

Use Value: Eliminates need for auxiliary supply while maintaining <20 dB(A) acoustic noise at 23°C ambient - validated per SPECpower SSJ2008.

LCD Television

Notebook Adapters

Use Scenario: Slim 200 W open-frame PSU for 55″ 4K TV with EMI-sensitive display interface and thermal-limited enclosure.

IC Role / Device Role / Timing Role: Digital PFC+LLC controller implementing PFC jitter and burst-mode frequency programming to shift EMI peaks outside critical bands.

Use Value: Reduces conducted EMI by 8 dBμV at 150 kHz–30 MHz without added filtering - passes CISPR-32 Class B with 3 dB margin.

Use Scenario: 90 W GaN-based notebook adapter requiring ultra-low standby power and fast transient recovery.

IC Role / Device Role / Timing Role: Combo controller regulating PFC output and LLC primary capacitor; uses SNSFB current regulation to maintain 100 μA opto-current during burst mode.

Use Value: Enables 0.03 W no-load consumption and <100 μs recovery from 20%→100% load step - exceeds DOE Level VI and EU CoC v5 Tier 2.

Equivalent & Alternatives

The following parts are listed as comparable options for similar PFC+LLC controller applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
UCC28070DWR	Analog dual-phase interleaved PFC + external LLC controller - lacks integrated LLC gate drivers, digital configurability, and V_CAP regulation.	Requires separate LLC driver IC and external microcontroller for mode sequencing - higher component count and longer development cycle.	Choose when legacy analog design flow or multi-phase PFC is required; not suitable for compact single-stage resonant topologies.
ICE5QSAG	Quasi-resonant flyback + PFC combo IC - uses frequency modulation instead of V_CAP control; no true LLC support or burst-mode optimization.	Targeted at sub-100 W adapters; cannot scale to >200 W with same efficiency or thermal profile as TEA2017ABT/2.	Prefer for cost-sensitive low-power adapters where LLC complexity is unnecessary; avoid for high-density 90–500 W systems.

Compared with UCC28070DWR and ICE5QSAG, the TEA2017ABT/2 uniquely combines digital configurability, integrated LLC drivers, V_CAP-based power regulation, and <75 mW no-load performance - making it the only option supporting scalable, GUI-tuned, single-package 90–500 W resonant power supplies meeting latest global energy standards.

Availability

TEA2017ABT/2 is available at Aetrix Electronics and suitable for desktop PC power supplies, gaming PSUs, LCD television main supplies, and notebook adapters requiring stable component supply, long-term lifecycle support, and compliance with Energy Star, DOE Level VI, and EU Eco-design directives.

Supply support for TEA2017ABT/2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer applications.

The TEA2017ABT/2 belongs to NXP's GreenChip™ AC-DC controller family, designed specifically for high-efficiency, digitally configurable resonant power conversion targeting next-generation energy-compliant power supplies.

FAQ

What is the primary function of the TEA2017ABT/2 in a power supply design?

The TEA2017ABT/2 serves as an integrated digital controller for combined DCM/QR PFC and LLC resonant converter stages. It manages both power factor correction and LLC half-bridge switching using a V_CAP-based regulation scheme, enabling high efficiency across full load range, programmable operating modes, and <75 mW no-load input power when paired with TEA2095T. Its hardware-state-machine architecture ensures deterministic real-time control without software overhead.

How does the TEA2017ABT/2 achieve zero-voltage switching (ZVS) in the LLC stage?

The TEA2017ABT/2 achieves ZVS through integrated valley detection on the HB pin, synchronized with resonant current sensing on SNSCURLLC. Its hardware state machine monitors the half-bridge node slope and current polarity to precisely time GATEHS and GATELS transitions - ensuring turn-on occurs at or near resonant current zero-crossing. This eliminates hard-switching losses and maintains ZVS across 10–100% load, confirmed by typical efficiency curves in Section 9 of the datasheet.

Can the TEA2017ABT/2 operate without an auxiliary winding on the LLC transformer?

Yes - the TEA2017ABT/2 includes an integrated high-voltage start-up circuit sourced from the DRAINPFC pin, allowing initial SUPIC charging directly from the PFC drain voltage. During normal operation, the auxiliary winding supplies SUPIC, but during burst mode or fault conditions, the internal HV current source resumes regulation of SUPIC to V_start(SUPIC). This dual-supply architecture eliminates dependency on auxiliary winding for start-up or protection recovery.

What protection features are configurable in the TEA2017ABT/2 and how are they implemented?

The TEA2017ABT/2 supports independent configuration of overcurrent (OCP), overpower (OPP), overtemperature (OTP), overvoltage (OVP), capacitive mode regulation (CMR), and inrush current (ICP) protections. Each is programmed via MTP memory with user-defined trip thresholds, timers, and response policies (latched, auto-restart, or restart-after-attempt). For example, OTP can be set to trigger at 145°C with 500 ms delay and latched shutdown, while OVP on SNSBOOST uses a 2.63 V threshold with hysteresis.

Is the TEA2017ABT/2 pin-compatible with other NXP GreenChip controllers like TEA2016 or TEA2095T?

No - the TEA2017ABT/2 has a unique 16-pin SO16 pinout optimized for dual-stage control, including dedicated SNSCAP, SNSCURLLC, and DRAINPFC pins not present in TEA2016 (PFC-only) or TEA2095T (LLC-driver-only). While TEA2017ABT/2 and TEA2095T are functionally complementary and commonly used together in 90–500 W designs, they are not pin-compatible; TEA2095T is a 14-pin SO14 device with different driver topology and sensing inputs.

TEA2017ABT/2Y Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: -

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: -

Applications:: Digital Power Controller

Voltage - Input:: -

Voltage - Supply:: 36V

Current - Supply:: 8 mA

Operating Temperature:: -40°C ~ 150°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SO

TEA2017ABT/2Y FAQ

1.How can I place an order for TEA2017ABT/2Y through Aetrix?

Please submit a Request for Quotation (RFQ) for TEA2017ABT/2Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TEA2017ABT/2Y reliable?

The price and inventory of TEA2017ABT/2Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TEA2017ABT/2Y is usually 5 days.

3.What payment methods are accepted for TEA2017ABT/2Y?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TEA2017ABT/2Y transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TEA2017ABT/2Y?

TEA2017ABT/2Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TEA2017ABT/2Y order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TEA2017ABT/2Y?

For technical support, including TEA2017ABT/2Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TEA2017ABT/2Y requirements.

6.How does Aetrix verify that TEA2017ABT/2Y is sourced from the original manufacturer or authorized distributors?

All TEA2017ABT/2Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TEA2017ABT/2Y meets industry standards.

7.What is the process for return or replacement of TEA2017ABT/2Y?

All TEA2017ABT/2Y units undergo pre-shipment inspection (PSI). If there is an issue with TEA2017ABT/2Y, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TEA2017ABT/2Y part is unused and in its original packaging.

Return procedure for TEA2017ABT/2Y:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…