NXP Semiconductors TFF11105HN/N1,118

Overview

TFF11105HN/N1,118 from NXP Semiconductors is a Ku-band frequency generator IC designed as a low-phase-noise local oscillator (LO) for VSAT transmitter and transceiver systems. It delivers RF output from 10.30 GHz to 10.80 GHz, achieves −97 dBc/Hz synthesizer phase noise at 100 kHz offset (with divider = 64), and supports reference inputs from 40 MHz to 675 MHz.

For engineers reviewing the TFF11105HN/N1,118 datasheet, TFF11105HN/N1,118 pinout, TFF11105HN/N1,118 application, or TFF11105HN/N1,118 equivalent, this device requires attention to its HVQFN24 package layout, third/fourth-order PLL architecture, VCO tuning voltage range (0.1–0.9 × VREGVCO), differential RF outputs (BUF1_P/N, BUF2_P/N), and IESS-308 compliance in LO circuits.

Technical Context

The TFF11105HN/N1,118 integrates a fully self-contained PLL subsystem with a VCO, PFD, charge pump (1 mA typical), and programmable divider (16/32/64/128/256). Its loop filter supports type-2 or type-3 configurations using internal 10 pF and 30 pF capacitors referenced to VREGVCO (2.7 V nominal).

It features dual differential RF output buffers (50 Ω collector impedance), on-chip regulated VCO supply (VREGVCO), and a lock detector (LCKDET) with 2.5 V CMOS output and 0.1 V hysteresis. Reference input is fully differential (IN(REF)_P/N), high-impedance, and AC-coupled, with divider settings controlled via three logic-configurable pins (NSL0–NSL2).

Key Specifications

Pinout & Package

HVQFN24 (SOT616-1), 4 × 4 × 0.85 mm body, thermally enhanced, no leads, 24-terminal package with exposed diepad for GND and thermal dissipation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LO generator applications.

Compared with LMX2594RHBR and HMC738LP4E, the TFF11105HN/N1,118 offers optimal balance of IESS-308 compliance, fixed-pin divider selection, and low-power (130 mA) operation in a compact HVQFN24 package - ideal for cost-sensitive, production-volume VSAT ODU designs requiring minimal external components.

Availability

TFF11105HN/N1,118 is available at Aetrix Electronics and suitable for Ku-band VSAT upconverters, microwave point-to-point radios, satellite communication hubs, and transceiver LO subsystems requiring stable component supply and long-term lifecycle support.

Supply support for TFF11105HN/N1,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and communications markets.

The TFF11105HN/N1,118 belongs to NXP's high-frequency RF synthesis product line, engineered specifically for Ku-band satellite infrastructure applications demanding low phase noise, high integration, and IESS-308 compliance.

FAQ

What is the guaranteed RF output frequency range of the TFF11105HN/N1,118?

The TFF11105HN/N1,118 guarantees an RF output frequency range of 10.30 GHz to 10.80 GHz. This Ku-band span is validated across temperature (−40 °C to +85 °C) and supply voltage (3.0–3.6 V) per Table 12 in the datasheet. The output remains stable under all specified divider settings and reference input conditions.

Does the TFF11105HN/N1,118 support differential or single-ended reference input?

The TFF11105HN/N1,118 supports only differential reference input via IN(REF)_P and IN(REF)_N pins. These are high-impedance, internally biased inputs requiring AC coupling. For single-ended sources, the unused input must be terminated to match the source impedance - as shown in Figure 8 of the datasheet.

How is the divider value configured on the TFF11105HN/N1,118?

The divider value on the TFF11105HN/N1,118 is set using three logic pins: NSL0 (pin 4), NSL1 (pin 5), and NSL2 (pin 6). Each pin is pulled up to VCC(DIV) internally (100 kΩ); connecting to GND sets "0", leaving open sets "1". Valid combinations yield divider values of 16, 32, 64, 128, or 256 - and must be fixed at power-up.

What is the purpose of the VREGVCO pin on the TFF11105HN/N1,118?

The VREGVCO pin (pin 1) provides a stabilized 2.7 V output used to bias the VCO's loop filter network. It serves as the reference node for the internal 10 pF and 30 pF capacitors connected to CPOUT and VTUNE, respectively. External loop filter components must be connected between VREGVCO and these pins per Figures 4 and 5.

Can the TFF11105HN/N1,118 drive a 50 Ω load directly?

Yes - the TFF11105HN/N1,118's RF output buffers (BUF1_P/N and BUF2_P/N) are designed for 50 Ω differential loads. Each output delivers −4 dBm into 50 Ω. If only one output is used, the complementary pin must be terminated to 50 Ω to maintain impedance balance and prevent reflections, as specified in Section 10.2.