NXP Semiconductors TFF11139HN/N1,118
- Part No.:
- TFF11139HN/N1,118
- Manufacturer:
- NXP Semiconductors
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
TFF11139HN/N1,118.pdf
- Description:
- IC FREQUENCY GENERATOR 24HVQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TFF11139HN/N1,118 from NXP Semiconductors is a Ku-band frequency generator IC designed as a low-phase-noise local oscillator (LO) for VSAT upconverters and transceivers. It delivers RF output from 13.80 GHz to 14.10 GHz, achieves −97 dBc/Hz synthesizer phase noise at 100 kHz offset (with divider = 64), and supports reference inputs from 54 MHz to 881 MHz. Its third- or fourth-order PLL architecture ensures stable LO synthesis compliant with IESS-308.
For engineers reviewing the TFF11139HN/N1,118 datasheet, TFF11139HN/N1,118 pinout, TFF11139HN/N1,118 application, or TFF11139HN/N1,118 equivalent, this device is critical for high-integrity satellite communication LO generation where phase noise, spurious suppression (−70 dBc), and differential RF output stability (±2 dB) directly impact uplink spectral purity and EVM performance.
Technical Context
The TFF11139HN/N1,118 integrates a VCO with 0.72 GHz/V tuning sensitivity (KO), a type-2 or type-3 PLL using internal 10 pF and 30 pF capacitors between CPOUT and VTUNE pins, and a bandgap-regulated VREGVCO (2.7 V typical) for loop filter biasing. Divider settings (16–256) are configured via three logic-controlled NSL pins with 100 kΩ pull-up resistors.
It features dual differential RF outputs (BUF1_P/N, BUF2_P/N) each delivering −6 dBm into 50 Ω, with −10 dB return loss and −10 dBc harmonic rejection. The lock detector (LCKDET) provides CMOS-compatible 2.5 V/0 V output with 7%–93% VREGVCO window thresholds and 0.1 V hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| RF Output Frequency | 13.80–14.10 GHz - precisely targets Ku-band uplink (14.0–14.5 GHz) after upconversion in VSAT transmitters. |
| Synthesizer Phase Noise | −97 dBc/Hz typ. @ 100 kHz offset (divider = 64) - meets IESS-308 spectral mask requirements for Intelsat-compliant VSAT systems. |
| Reference Input Range | 54–881 MHz - enables use of common crystal oscillators or synthesizers; actual reference freq = RF freq / divider value. |
| Output Power & Stability | −6 dBm ±2 dB per differential output - sufficient drive level for mixer LO ports without external amplification; stable across temperature. |
| VCO Tuning Sensitivity | 0.72 GHz/V (KO) - defines loop bandwidth trade-off and tuning linearity; used with external loop filter components per Table 5. |
| Supply Current | 100–130 mA @ 3.3 V - determines thermal design margin and power rail sizing for compact VSAT RF modules. |
| Reference Spurious Suppression | −70 dBc @ divider = 256 - minimizes reference feedthrough that could degrade adjacent-channel interference in multi-carrier VSAT operation. |
Pinout & Package
HVQFN24 package (SOT616-1): 4 mm × 4 mm × 0.85 mm body, thermally enhanced, no leads, 24 terminals with exposed diepad for grounding and thermal dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VREGVCO (1) | VCO regulator output | Provides stable 2.7 V reference for loop filter; connect external R/C components here for type-2/type-3 PLL filtering. |
| CPOUT (2) | Charge pump output | Drives loop filter; internally connected to 10 pF cap to VREGVCO; interconnect with VTUNE for type-2 configuration. |
| VTUNE (3) | VCO tuning voltage input | Accepts 0.1–0.9 × VREGVCO range; internally filtered by 30 pF cap to VREGVCO; sets VCO frequency. |
| NSL0–NSL2 (4–6) | Divider select bits | Three-pin binary control (LSB–MSB) for divider values 16/32/64/128/256; open = logic 1, GND = logic 0; fixed at startup only. |
| LCKDET (7) | Lock detect output | CMOS-level signal: 2.5 V = locked, 0 V = unlocked; uses window detector on VTUNE with 7%–93% VREGVCO thresholds. |
| IN(REF)_P/N (9–10) | Differential reference input | High-impedance AC-coupled inputs; require matched termination; support single-ended use with proper biasing. |
| BUF1_P/N, BUF2_P/N (11,14,20,21,22,23) | Differential RF outputs | Each pair delivers −6 dBm into 50 Ω; unused outputs must be terminated to 50 Ω to maintain impedance match and isolation. |
Key Features
| Feature | Design Value |
|---|---|
| IESS-308–compliant phase noise | Validated at −97 dBc/Hz @ 100 kHz offset with divider = 64 and −149 dBc/Hz reference noise - ensures regulatory acceptance in Intelsat networks. |
| Integrated VCO regulator (VREGVCO) | Stable 2.7 V output eliminates need for external LDO; reduces component count and improves loop filter PSRR in noisy RF environments. |
| Configurable PLL order (type-2/type-3) | Supports both loop filter topologies via external R/C selection; type-3 enables higher loop bandwidth for faster lock time without sacrificing stability. |
| Dual differential RF outputs | Two independent 50 Ω differential buffers allow simultaneous drive of I/Q mixers or redundant paths - improves system reliability in mission-critical VSAT links. |
| ESD-protected interface | 2.5 kV HBM rating on all pins - protects against handling damage during assembly of high-frequency RF modules where trace routing limits guard ring options. |
Applications
| VSAT Upconverter LO | Ku-Band Transceiver LO |
|---|---|
|
Use Scenario: Generating clean local oscillator signals for Ku-band upconversion in 1.2 m VSAT terminals operating in 14.0–14.5 GHz uplink bands. IC Role / Device Role / Timing Role: Primary LO source driving quadrature mixer inputs; replaces discrete VCO + PLL IC combinations. Use Value: Delivers −97 dBc/Hz phase noise at 100 kHz offset, enabling <−35 dBc ACLR in 32APSK modulated carriers per IESS-308. |
Use Scenario: Providing synchronized LO signals to both transmit and receive paths in full-duplex Ku-band transceivers for maritime or mobility terminals. IC Role / Device Role / Timing Role: Dual-output LO generator supplying independent but phase-coherent signals to Tx and Rx mixers. Use Value: Two matched differential outputs (BUF1 and BUF2) reduce inter-path skew and eliminate need for external splitters or amplifiers. |
| Intelsat Network Compliant Terminal | Low-Spurious Satellite Modem |
|
Use Scenario: Enabling certification-ready VSAT hardware for Intelsat's global satellite network requiring strict adherence to IESS-308 spectral masks. IC Role / Device Role / Timing Role: Certified LO generator meeting phase noise, spurious, and harmonic specifications defined in IESS-308 Annex A. Use Value: −70 dBc reference spurious suppression and −10 dBc harmonic rejection ensure compliance without additional filtering stages. |
Use Scenario: Serving as the core LO in high-order QAM satellite modems where LO phase noise directly impacts EVM floor and throughput. IC Role / Device Role / Timing Role: High-stability synthesizer generating carrier tones for 256-QAM and 1024-QAM uplinks. Use Value: VCO KO of 0.72 GHz/V enables precise loop filter optimization for <1° RMS jitter at symbol rates up to 45 Msps. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LO generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HMC738LP4E | Wider VCO range (12.5–14.5 GHz); higher supply current (180 mA); no integrated VREGVCO; requires external loop filter op-amps. | Supports broader Ku-band coverage but lacks IESS-308 validation; better suited for lab-grade test equipment than certified VSAT terminals. | Select when wider frequency agility is needed and external regulation/filtering is acceptable; not drop-in for TFF11139HN/N1,118 footprint or bias scheme. |
| ADF4371BCPZ | Integrated fractional-N synthesizer with SPI interface; lower max RF output (13.6 GHz); −111 dBc/Hz phase noise at 100 kHz but requires external VCO. | Enables programmable LO stepping and fine resolution; intended for software-defined radios rather than fixed-frequency VSAT upconverters. | Select when digital reconfiguration and sub-Hz frequency resolution are required; incompatible with TFF11139HN/N1,118's analog divider control and VCO integration. |
Compared with HMC738LP4E and ADF4371BCPZ, the TFF11139HN/N1,118 offers purpose-built IESS-308 compliance, integrated VCO regulation, and dual differential outputs - making it uniquely optimized for production VSAT upconverters where certification, board space, and supply simplicity are prioritized over programmability or extended frequency range.
Availability
TFF11139HN/N1,118 is available at Aetrix Electronics and suitable for VSAT upconverter designs, Ku-band transceiver development, and Intelsat-compliant terminal manufacturing requiring stable component supply and long-term obsolescence management.
Supply support for TFF11139HN/N1,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and communications markets, with deep expertise in RF and mixed-signal IC design.
The TFF11139HN/N1,118 belongs to NXP's Ku-band LO generator product line, engineered specifically for high-reliability satellite communication infrastructure where phase noise, spurious performance, and regulatory compliance are non-negotiable.
FAQ
What is the guaranteed RF output frequency range of the TFF11139HN/N1,118?
The TFF11139HN/N1,118 guarantees an RF output frequency range of 13.80 GHz to 14.10 GHz under specified operating conditions (Tamb = −40 °C to +85 °C, VCC = 3.3 V). This range is validated for Ku-band VSAT upconverter applications and aligns with IESS-308 requirements for Intelsat network compatibility. Operation outside this band is not characterized or supported.
How does the TFF11139HN/N1,118 achieve IESS-308 phase noise compliance?
The TFF11139HN/N1,118 achieves IESS-308 compliance through its optimized third- or fourth-order PLL architecture, integrated VREGVCO-stabilized loop filter interface, and VCO design yielding −97 dBc/Hz synthesizer phase noise at 100 kHz offset (with divider = 64 and −149 dBc/Hz reference noise). Compliance is verified per Table 12 and Figure 4/5 loop filter configurations in the official NXP datasheet Rev. 1.
Can the TFF11139HN/N1,118 operate with a single-ended reference input?
Yes, the TFF11139HN/N1,118 supports single-ended reference input via IN(REF)_P (pin 9), provided IN(REF)_N (pin 10) is terminated to the same impedance as the source (e.g., 50 Ω to ground), as shown in Figure 8 of the datasheet. The differential input stage remains biased correctly, and AC coupling is mandatory for both configurations.
What are the thermal limitations and PCB layout recommendations for the TFF11139HN/N1,118?
The TFF11139HN/N1,118 has a junction-to-solder-point thermal resistance (Rth(j-sp)) of 25 K/W and a maximum junction temperature of +125 °C. PCB layout must expose the HVQFN24 diepad (pins 8, 11, 14, 17, 19, 24) to a minimum 100 mm² copper pour with ≥4 thermal vias (0.3 mm diameter) to an inner ground plane. Avoid routing high-speed traces under the IC body.
Is the TFF11139HN/N1,118 pin-compatible with other NXP Ku-band LO generators?
No, the TFF11139HN/N1,118 is not pin-compatible with other NXP Ku-band LO generators such as the TFF11138 or TFF11140. Its HVQFN24 pinout (SOT616-1), dual-buffer architecture, and dedicated NSL divider control pins are unique to this device. Migration requires full schematic and layout revision, including loop filter and output matching network redesign.
TFF11139HN/N1,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- PLL:
- Yes
- Main Purpose:
- Ku band VSAT applications
- Input:
- Clock
- Output:
- Clock
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:4
- Differential - Input:Output:
- Yes/No
- Frequency - Max:
- 14.1GHz
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-HVQFN (4x4)
TFF11139HN/N1,118 FAQ
1.How can I place an order for TFF11139HN/N1,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for TFF11139HN/N1,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TFF11139HN/N1,118 reliable?
The price and inventory of TFF11139HN/N1,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TFF11139HN/N1,118 is usually 5 days.
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Once your TFF11139HN/N1,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TFF11139HN/N1,118?
For technical support, including TFF11139HN/N1,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TFF11139HN/N1,118 requirements.
6.How does Aetrix verify that TFF11139HN/N1,118 is sourced from the original manufacturer or authorized distributors?
All TFF11139HN/N1,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TFF11139HN/N1,118 meets industry standards.
7.What is the process for return or replacement of TFF11139HN/N1,118?
All TFF11139HN/N1,118 units undergo pre-shipment inspection (PSI). If there is an issue with TFF11139HN/N1,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TFF11139HN/N1,118 part is unused and in its original packaging.
Return procedure for TFF11139HN/N1,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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