Texas Instruments THS10064CDA

Overview

THS10064CDA from Texas Instruments is a 10-bit, 6 MSPS simultaneous-sampling analog-to-digital converter (ADC) with four analog inputs, internal 1.5 V/3.5 V voltage references (±5% accuracy, 50 ppm/°C), and integrated 16-word FIFO. It operates on a single 5-V analog supply and supports both single-ended and differential input configurations for radar, communications, and high-speed DSP front-end applications.

For engineers reviewing the THS10064CDA datasheet, THS10064CDA pinout, THS10064CDA application, or THS10064CDA equivalent, key selection considerations include simultaneous 4-channel sampling capability, 59 dB SINAD at 2 MHz input, 6 MSPS maximum per-channel rate in continuous mode, TSSOP-32 package compatibility, and glueless interface to DSPs and microcontrollers.

Technical Context

The THS10064CDA employs a multistage pipelined ADC architecture with output error correction logic to guarantee no missing codes across 0°C to 70°C. It supports two conversion modes: single-conversion (internally clocked, up to 3 MSPS per channel) and continuous-conversion (externally clocked, up to 6 MSPS per channel with 1 channel).

Input configuration is programmable via control registers-each of the four analog inputs (AINP/AINM, BINP/BINM) can be set as single-ended or differential. The integrated FIFO buffers data for asynchronous processor reads, and DATA_AV signaling supports interrupt-driven transfers with configurable trigger levels and polarity.

Key Specifications

Pinout & Package

TSSOP-32 package (DA suffix), 7.0 mm × 12.0 mm body, 0.65 mm pitch, exposed thermal pad not electrically connected.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed simultaneous-sampling ADC applications.

Compared with THS1206CDA and ADS8364IPAG, the THS10064CDA uniquely balances 10-bit resolution, 6 MSPS per-channel speed, parallel interface, and integrated FIFO-making it optimal for real-time embedded systems where latency, determinism, and interface simplicity are critical.

Availability

THS10064CDA is available at Aetrix Electronics and suitable for radar signal processing, industrial motor control, and automotive sensor fusion requiring stable component supply across extended production lifecycles.

Supply support for THS10064CDA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with broad industrial and automotive design-in support.

The THS10064CDA belongs to TI's high-speed data acquisition product line, engineered for real-time signal digitization in radar, communications, and motion control systems demanding simultaneous multi-channel sampling and low-latency interface.

FAQ

What is the maximum sampling rate per channel for THS10064CDA in continuous conversion mode?

The THS10064CDA achieves 6 MSPS per channel when only one analog input is selected in continuous conversion mode. With two channels, the rate drops to 3 MSPS per channel; with three, to 2 MSPS; and with four, to 1.5 MSPS. This scaling results from the fixed 6 MSPS total pipeline throughput distributed across active channels. The THS10064CDA datasheet Table 1 confirms these values under recommended operating conditions.

Does THS10064CDA support differential input configurations?

Yes, the THS10064CDA supports differential inputs on two dedicated pairs: AINP/AINM and BINP/BINM. Each pair can be configured independently as differential or single-ended via internal control registers. In differential mode, the device achieves 59 dB SINAD at 2 MHz and 96 MHz full-power bandwidth-superior to single-ended performance-making THS10064CDA suitable for noise-sensitive applications like motor current sensing and RF receiver chains.

How does the integrated FIFO in THS10064CDA improve system-level data handling?

The THS10064CDA integrates a 16-word deep FIFO that decouples ADC conversion from host processor read timing. This allows burst sampling without immediate CPU servicing, reduces interrupt frequency, and prevents data loss during processor latency. DATA_AV signaling-configurable as level or pulse-enables efficient polling or interrupt-driven reads. For example, in a radar application, the THS10064CDA FIFO absorbs multiple chirp returns before host DMA transfer, simplifying real-time processing architecture.

Can THS10064CDA operate with a 3.3-V digital supply while using a 5-V analog supply?

Yes, the THS10064CDA supports independent supply domains: AVDD = 5 V (analog), DVDD = 3.3 V (digital I/O), and BVDD = 3.3 V (output buffers). This mixed-supply operation is explicitly specified in the Recommended Operating Conditions table (Section 2), enabling direct interfacing with 3.3-V FPGAs or microcontrollers without level shifters. The THS10064CDA maintains full AC performance-including 59 dB SINAD-under this configuration, as verified in Electrical Characteristics testing.

Is THS10064CDA pin-compatible with any other Texas Instruments ADCs?

Yes, the THS10064CDA is pin-compatible with the 12-bit THS1206 family (e.g., THS1206CDA) in the same TSSOP-32 package. This allows resolution upgrades without PCB redesign. However, functional differences exist: THS1206 offers higher resolution but lower per-channel throughput in multi-channel mode and higher power consumption. System validation is required before substitution, as THS10064CDA and THS1206 differ in timing parameters, reference structure, and control register mapping.