Texas Instruments THS10064CDAG4

Overview

THS10064CDAG4 from Texas Instruments is a 10-bit, 6 MSPS simultaneous-sampling analog-to-digital converter with four analog inputs, internal 1.5 V/3.5 V voltage references (50 ppm/°C), and integrated 16-word FIFO. It operates on a single 5-V analog supply and supports both single-ended and differential input configurations for radar, communications, and high-speed DSP front-end systems.

For engineers reviewing the THS10064CDAG4 datasheet, THS10064CDAG4 pinout, THS10064CDAG4 application, or THS10064CDAG4 equivalent, key selection criteria include simultaneous 4-channel sampling capability, ±1 LSB DNL, 59 dB SINAD at 2 MHz input, 3-V/5-V digital interface compatibility, and TSSOP-32 package with glueless DSP interface support.

Technical Context

The THS10064CDAG4 employs a multistage pipelined ADC architecture with output error correction logic to guarantee no missing codes across temperature. Its dual conversion modes-single-conversion (internally clocked) and continuous-conversion (externally clocked via CONV_CLK)-enable flexible timing control in real-time acquisition systems.

Four analog inputs (AINP/AINM, BINP/BINM) are sampled simultaneously and configurable per channel as single-ended or differential. Internal reference voltages (REFP = 3.5 V, REFM = 1.5 V) provide ±5% accuracy and can be replaced by external references for improved DC precision.

Key Specifications

Pinout & Package

TSSOP-32 package with 0.65 mm pitch, 10.1 mm × 5.1 mm body, and exposed thermal pad (not electrically connected). RoHS-compliant, moisture sensitivity level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed simultaneous-sampling ADC applications.

Compared with THS10064CDAG4, THS1206CDAG4 trades FIFO and lower power for 2 extra bits of resolution, while ADS8364IPAG replaces parallel throughput with serial simplicity and precision at 1/24th the sampling rate-making each suitable for distinct trade-off points in acquisition system design.

Availability

THS10064CDAG4 is available at Aetrix Electronics and suitable for radar signal acquisition, industrial motor control feedback, and automotive ADAS sensor fusion requiring stable component supply across extended temperature ranges.

Supply support for THS10064CDAG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of heritage in high-performance data converters.

The THS10064CDAG4 belongs to TI's high-speed simultaneous-sampling ADC product line, designed specifically for phase-coherent multi-channel digitization in radar, communications, and real-time control systems.

FAQ

What is the maximum sampling rate per channel for THS10064CDAG4 in continuous conversion mode?

The THS10064CDAG4 achieves 6 MSPS per channel when sampling only one analog input in continuous conversion mode. With two inputs, the rate drops to 3 MSPS per channel; three inputs yield 2 MSPS; and four inputs operate at 1.5 MSPS per channel. This scaling results directly from the fixed 6 MSPS total pipeline throughput distributed across active channels.

Does THS10064CDAG4 support differential input configurations?

Yes, THS10064CDAG4 supports differential inputs on both Channel A (AINP/AINM) and Channel B (BINP/BINM). Each pair can be independently configured as differential or single-ended, and the device simultaneously samples all selected inputs-enabling true phase-matched acquisition of up to two differential signals.

What reference voltage options does THS10064CDAG4 provide?

THS10064CDAG4 includes an internal reference generating 3.5 V (REFP) and 1.5 V (REFM) with ±5% accuracy and 50 ppm/°C drift. It also accepts external references applied to REFP and REFM pins, selectable via control register 0-allowing users to optimize dc accuracy and temperature stability for specific application requirements.

How does the integrated FIFO in THS10064CDAG4 improve system design?

The 16-word deep FIFO in THS10064CDAG4 decouples ADC conversion timing from processor read timing, absorbing bursts of data and reducing interrupt load. It enables reliable data capture even with variable processor latency, and supports trigger-level programmability (1–12) to balance FIFO fill depth against DATA_AV assertion delay in real-time systems.

Is THS10064CDAG4 pin-compatible with other devices in its family?

Yes, THS10064CDAG4 is pin-compatible with the 12-bit THS1206 series (e.g., THS1206CDAG4) in the same TSSOP-32 package. This allows resolution upgrades without PCB redesign, though users must verify timing margins and power delivery since THS1206 draws higher current and lacks the THS10064CDAG4's integrated FIFO.