Texas Instruments THS10064CDAR

Overview

THS10064CDAR from Texas Instruments is a 10-bit, 6 MSPS simultaneous-sampling analog-to-digital converter (ADC) with four analog inputs, internal 2.5 V reference output, 16-word FIFO, and TSSOP-32 package. It supports single-ended or differential input configurations, operates on 5-V analog/3.3-V digital supplies, and delivers 59 dB SINAD at 2 MHz for radar front-end acquisition.

For engineers reviewing the THS10064CDAR datasheet, THS10064CDAR pinout, THS10064CDAR application, or THS10064CDAR equivalent, key selection criteria include simultaneous 4-channel sampling capability, internal reference accuracy (±5%, 50 ppm/°C), FIFO depth (16 words), power dissipation (216 mW max), and compatibility with glueless DSP/microcontroller interfaces.

Technical Context

The THS10064CDAR employs a multistage pipelined ADC architecture with output error correction logic to guarantee no missing codes across temperature. Its dual conversion modes-single-conversion (internally clocked) and continuous-conversion (externally clocked via CONV_CLK)-enable flexible timing control in high-speed data acquisition systems.

Simultaneous sampling of up to four channels is implemented using four independent sample-and-hold amplifiers, configurable per channel as single-ended or differential. Internal voltage references (VREFP = 3.5 V, VREFM = 1.5 V, REFOUT = 2.5 V) support precise full-scale definition, while external reference inputs (REFP/REFM) allow dc accuracy optimization.

Key Specifications

Pinout & Package

TSSOP-32 package with 0.65 mm pitch, 10.1 mm × 5.1 mm body, and exposed thermal pad (not electrically connected). RoHS-compliant, moisture sensitivity level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed simultaneous-sampling ADC applications.

Compared with THS10064CDAR, THS1206CDAR trades sampling speed for resolution and shares identical pinout, while ADS8364IPAG offers higher precision at significantly lower speed and requires redesign of interface logic and PCB layout.

Availability

THS10064CDAR is available at Aetrix Electronics and suitable for radar signal acquisition, communications receiver front-ends, and industrial motor control systems requiring stable component supply and long-term obsolescence management.

Supply support for THS10064CDAR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies for industrial, automotive, and communications markets.

The THS10064CDAR belongs to TI's high-speed data acquisition product line, designed specifically for phase-coherent multi-channel digitization in radar, test equipment, and real-time control systems.

FAQ

What is the maximum sampling rate per channel for THS10064CDAR in continuous conversion mode?

The THS10064CDAR achieves 6 MSPS per channel when sampling a single analog input in continuous conversion mode. With two channels, the rate drops to 3 MSPS per channel; with three, to 2 MSPS; and with four, to 1.5 MSPS - governed by pipeline latency and FIFO management. This scaling is explicitly defined in Table 1 of the THS10064CDAR datasheet and reflects fixed architectural constraints, not programmable limits.

Does THS10064CDAR support differential input configurations?

Yes, THS10064CDAR supports differential inputs on AINP/AINM and BINP/BINM pairs. Each pair can be independently configured as differential or single-ended via control register settings. In differential mode, it achieves 59 dB SINAD and 65 dB SFDR at 2 MHz - 1–2 dB better than single-ended operation - making THS10064CDAR suitable for noise-sensitive applications like communications receivers.

How does the internal FIFO in THS10064CDAR improve system-level data handling?

The THS10064CDAR's 16-word deep FIFO decouples ADC conversion timing from processor readout latency. When DATA_AV asserts, up to 16 samples are guaranteed available for burst read - reducing interrupt frequency and preventing data loss during ISR execution. This is especially valuable in real-time systems using THS10064CDAR for radar echo capture where burst intervals must align precisely with pulse repetition timing.

Can THS10064CDAR operate with an external reference voltage?

Yes, THS10064CDAR accepts external references via REFP and REFM pins. When control register bit 0 is set, the internal 3.5 V / 1.5 V reference is disabled and external voltages define full-scale range. This allows optimization of dc accuracy and temperature drift - for example, using a precision 2.5 V reference improves THS10064CDAR offset error to ±2 LSB over temperature versus ±5 LSB with internal reference.

What are the supply voltage requirements for THS10064CDAR?

THS10064CDAR requires AVDD = 4.75–5.25 V (analog), DVDD = 3.0–5.25 V (digital I/O), and BVDD = 3.0–5.25 V (buffer supply). AGND, DGND, and BGND must be separated and tied at a single point. Operation outside these ranges risks parametric degradation or damage - for instance, DVDD < 3.0 V disables the parallel interface, and AVDD > 5.25 V violates absolute maximum ratings.