Texas Instruments THS10064IDA

Overview

THS10064IDA from Texas Instruments is a 10-bit, 6 MSPS simultaneous-sampling analog-to-digital converter (ADC) with four analog inputs, 5-V analog single-supply operation, internal 1.5 V/3.5 V references (±5% accuracy, 50 ppm/°C), and integrated 16-word FIFO. It supports configurable single-ended or differential input pairs and targets high-speed DSP front-ends in radar and communications systems.

For engineers reviewing the THS10064IDA datasheet, THS10064IDA pinout, THS10064IDA application, or THS10064IDA equivalent, key selection criteria include simultaneous 4-channel sampling capability, ±1 LSB DNL, 59 dB SINAD at 2 MHz, TSSOP-32 package compatibility, and support for both single-conversion and continuous-conversion modes with external or internal clocking.

Technical Context

The THS10064IDA employs a multistage pipelined ADC architecture with output error correction logic to guarantee no missing codes across –40°C to +85°C. Its four analog inputs are sampled simultaneously and can be independently configured as single-ended or differential pairs via internal control registers.

It operates in two conversion modes: single-conversion mode (triggered by CONVST, internally clocked) and continuous-conversion mode (driven by external CONV_CLK up to 6 MHz). The integrated 16-word FIFO buffers converted data to decouple sampling from processor read timing, supporting glueless interface to DSPs and microcontrollers.

Key Specifications

Pinout & Package

TSSOP-32 package (DA suffix), 7.0 mm × 12.0 mm body, 0.65 mm pitch, exposed thermal pad (not electrically connected).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed simultaneous-sampling ADC applications.

Compared with THS10064IDA, THS1206IDA offers higher resolution at lower speed and identical packaging, while ADS8556IPMR trades speed and interface compatibility for 16-bit precision and six channels - neither is pin-compatible, requiring PCB and firmware redesign.

Availability

THS10064IDA is available at Aetrix Electronics and suitable for radar signal acquisition, communications baseband processing, and industrial motor control requiring stable component supply across extended temperature ranges.

Supply support for THS10064IDA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of heritage in high-performance data converters and signal chain solutions.

The THS10064IDA belongs to TI's high-speed pipeline ADC product line, designed specifically for phase-coherent multi-channel digitization in radar, communications, and real-time control systems demanding simultaneous sampling and low-latency interface.

FAQ

What is the maximum sampling rate per channel for THS10064IDA in continuous conversion mode?

The THS10064IDA achieves 6 MSPS per channel when sampling a single analog input in continuous conversion mode. With two channels, the rate drops to 3 MSPS per channel; three channels yield 2 MSPS; and four channels operate at 1.5 MSPS per channel - governed by the internal pipeline latency and FIFO depth. This scaling is explicitly defined in Table 1 of the THS10064IDA datasheet.

Does THS10064IDA support differential input configurations?

Yes, THS10064IDA supports differential inputs on two dedicated pairs: AINP/AINM and BINP/BINM. Each pair can be configured independently as differential or single-ended via internal control registers. In differential mode, it delivers 59 dB SINAD and 65 dB SFDR at 2 MHz, with full-power bandwidth of 96 MHz - critical for noise-rejecting applications like motor current sensing or RF IF sampling.

What reference voltage options does THS10064IDA provide?

THS10064IDA includes an internal reference generating 1.5 V (REFM) and 3.5 V (REFP) with ±5% accuracy and 50 ppm/°C drift. It also supports external reference via REFP and REFM pins, programmable through control register 0. The REFOUT pin provides a buffered 2.5 V output (±25 mV) with 250 µA drive capability, usable as a stable system reference for auxiliary circuitry alongside the THS10064IDA.

How does the integrated FIFO in THS10064IDA improve system design?

The THS10064IDA's 16-word deep FIFO decouples high-speed sampling from host processor read timing, reducing interrupt load and enabling burst transfers. DATA_AV asserts when FIFO reaches a user-programmable trigger level (1–12 words), allowing efficient DMA or polled reads without losing samples. This eliminates the need for external memory buffers and simplifies timing-critical interfaces to DSPs or microcontrollers.

Is THS10064IDA pin-compatible with other devices in its family?

Yes, THS10064IDA is pin-compatible with the 12-bit THS1206 series (e.g., THS1206IDA) in the TSSOP-32 (DA) package, sharing identical pin assignments for power, ground, analog inputs, data bus, and control signals. However, register maps and timing parameters differ - firmware must be adapted for resolution, conversion modes, and FIFO behavior despite mechanical and electrical pinout compatibility.