Texas Instruments THS10064IDAG4

Overview

THS10064IDAG4 from Texas Instruments is a 10-bit, 6 MSPS simultaneous-sampling analog-to-digital converter (ADC) with four analog inputs, internal 1.5 V/3.5 V voltage references (±5% accuracy, 50 ppm/°C), and integrated 16-word FIFO. It operates on a single 5-V analog supply and supports both single-ended and differential input configurations for radar, communications, and high-speed DSP front-end systems.

For engineers reviewing the THS10064IDAG4 datasheet, THS10064IDAG4 pinout, THS10064IDAG4 application, or THS10064IDAG4 equivalent, key selection criteria include simultaneous 4-channel sampling capability, 59 dB SINAD at 2 MHz input, ±1 LSB DNL, glueless DSP interface compatibility, and TSSOP-32 package with verified pin mapping per TI SLAS255B.

Technical Context

The THS10064IDAG4 employs a multistage pipelined ADC architecture with output error correction logic to guarantee no missing codes across –40°C to +85°C. Its dual conversion modes-internally clocked single-conversion mode and externally clocked continuous-conversion mode-enable flexible timing control for real-time acquisition systems.

Simultaneous sampling of up to four channels is implemented via configurable S/H stages and a programmable input MUX supporting mixed single-ended/differential topologies. The integrated FIFO buffers converted data for asynchronous processor readout, while internal reference voltages (REFP = 3.5 V, REFM = 1.5 V) and REFOUT = 2.5 V provide stable scaling without external components.

Key Specifications

Pinout & Package

TSSOP-32 package (DA suffix), 7.0 mm × 12.0 mm body, 0.65 mm pitch, exposed thermal pad (not electrically connected). RoHS-compliant, moisture sensitivity level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar simultaneous-sampling ADC applications.

Compared with THS10064IDAG4, THS1206IDAG4 trades FIFO and power efficiency for resolution, while ADS8556IPMR sacrifices speed and integration for precision-making THS10064IDAG4 optimal for cost-sensitive, thermally constrained, multi-channel real-time systems.

Availability

THS10064IDAG4 is available at Aetrix Electronics and suitable for radar signal acquisition, communications baseband processing, and industrial motor control applications requiring stable component supply across extended temperature ranges.

Supply support for THS10064IDAG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 50 years of innovation in data converters and signal chain solutions.

The THS10064IDAG4 belongs to TI's high-speed precision ADC product line, designed specifically for phase-coherent, multi-channel acquisition in radar, test equipment, and real-time control systems.

FAQ

What is the operating temperature range for the THS10064IDAG4?

The THS10064IDAG4 is characterized for operation from –40°C to +85°C (industrial grade), matching the THS10064I specification. This range is validated per TI SLAS255B and supports deployment in automotive engine compartments, outdoor radar enclosures, and factory-floor motor drives without derating.

Does the THS10064IDAG4 require an external reference voltage?

No, the THS10064IDAG4 includes internal voltage references (VREFP = 3.5 V, VREFM = 1.5 V, REFOUT = 2.5 V) with ±5% initial accuracy and 50 ppm/°C drift. An external reference may be used via REFP/REFM pins only if tighter dc accuracy or custom full-scale range is required-otherwise, the internal reference eliminates BOM and layout complexity.

How does the FIFO function in the THS10064IDAG4?

The THS10064IDAG4 integrates a 16-word deep × 10-bit FIFO that stores converted samples before host readout. DATA_AV asserts when FIFO contains data, enabling interrupt-driven transfers. The FIFO decouples sampling timing from processor latency, allowing burst reads without data loss-even during CPU-intensive operations.

Can the THS10064IDAG4 sample differential and single-ended inputs simultaneously?

Yes, the THS10064IDAG4 supports mixed configurations: e.g., one differential pair (AINP/AINM) and two single-ended inputs (BINP, CINP) can be sampled simultaneously. Input selection and mode configuration are controlled via internal registers RA0/RA1 and control register 0, with no hardware reconfiguration needed.

What is the maximum achievable throughput when using all four analog inputs?

In continuous conversion mode, the THS10064IDAG4 achieves 1.5 MSPS per channel when all four inputs are active-maintaining full 10-bit resolution and 59 dB SINAD. In single conversion mode, the rate drops to 1.2 MSPS per channel due to internal oscillator timing constraints, as specified in Table 2 of SLAS255B.