Texas Instruments THS1206QDAR
- Part No.:
- THS1206QDAR
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-TSSOP (0.240", 6.10mm Width)
- Datasheet:
-
THS1206QDAR.pdf
- Description:
- IC ADC 12BIT PIPELINED 32TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,826
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
THS1206QDAR from Texas Instruments is a 12-bit, 6 MSPS simultaneous-sampling analog-to-digital converter (ADC) with four analog inputs, single-supply 5-V analog operation, integrated 16-word FIFO, and internal 2.5-V reference output. It supports configurable single-ended or differential input modes and operates across –40°C to 125°C for automotive applications.
For engineers reviewing the THS1206QDAR datasheet, THS1206QDAR pinout, THS1206QDAR application, or THS1206QDAR equivalent, key selection considerations include simultaneous 4-channel sampling capability, ±1 LSB DNL, 68 dB SNR at 2 MHz, TSSOP-32 package compatibility, and automotive-grade temperature range validation.
Technical Context
The THS1206QDAR employs a multistage pipelined ADC architecture with output error correction logic to guarantee no missing codes over its full –40°C to 125°C operating range. Its dual conversion modes-internally clocked single-conversion and externally clocked continuous-conversion-enable flexible system integration with DSPs or microcontrollers.
It integrates programmable control registers, auto-scan mode for 2–4 inputs, and a glueless parallel μC/DSP interface with 12-bit bidirectional data bus (D0–D11), chip select (CS0/CS1), and configurable RD/WR control. The internal voltage reference provides ±5% accuracy and 50 ppm/°C drift, while external reference support enables precision calibration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit - delivers 4096 discrete digital levels for high-fidelity signal digitization in radar and communications front-ends. |
| Sampling Rate | 6 MSPS maximum per channel in continuous mode - supports real-time capture of wideband signals up to 54 MHz small-signal bandwidth (single-ended). |
| Differential Nonlinearity | ±1 LSB - ensures monotonic transfer function critical for closed-loop control and measurement integrity. |
| Signal-to-Noise Ratio | 68 dB at fI = 2 MHz - enables >11-bit effective resolution in single-ended mode for high-dynamic-range acquisition. |
| Operating Temperature | –40°C to +125°C - qualified for under-hood automotive environments per AEC-Q100 stress requirements. |
| Supply Voltage | AVDD = 4.75–5.25 V; DVDD/BVDD = 3–5.25 V - supports mixed-voltage interfacing with 3.3-V or 5-V logic domains. |
| Internal Reference | REFOUT = 2.5 V ±2.5% (Q suffix), 50 ppm/°C TC - reduces BOM count and improves dc accuracy without external reference circuitry. |
Pinout & Package
TSSOP-32 (DA package), 7.0 mm × 12.0 mm body, 0.65 mm pitch, thermally enhanced with exposed pad (not electrically connected). Pin 1 marked by dot; pin numbering follows standard top-view counterclockwise convention.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AINP / AINM / BINP / BINM (Pins 32, 31, 30, 29) | Analog input pairs | Support simultaneous sampling of two differential channels or four single-ended channels; input capacitance 15 pF limits source impedance impact. |
| CONV_CLK / CONVST (Pin 15) | Mode-shared control input | Functions as external clock input in continuous mode or conversion start trigger in single mode - eliminates need for separate timing control lines. |
| DATA_AV (Pin 16) | FIFO status output | Indicates valid data availability in FIFO; configurable as active-high/low pulse or static level - simplifies interrupt-driven or polling-based host readout. |
| D0–D11 (Pins 1–6, 9–14) | 12-bit bidirectional data bus | Includes multiplexed address lines RA0/RA1 (D10/D11) for control register access - enables compact 8- or 16-bit bus interfacing without external address latches. |
| REFP / REFM / REFOUT / REFIN (Pins 26, 25, 27, 28) | Reference subsystem | Internal 3.5 V/1.5 V reference pair; REFOUT supplies stable 2.5 V ±2.5% reference; REFIN accepts common-mode bias - supports both ratiometric and absolute measurement topologies. |
Key Features
| Feature | Design Value |
|---|---|
| Simultaneous 4-channel sampling | Enables phase-coherent acquisition across multiple sensors (e.g., motor current/voltage, position feedback) without time skew - essential for vector control and power quality analysis. |
| Integrated 16-word FIFO | Offloads host processor by buffering up to 16 samples; DATA_AV signaling allows deterministic read scheduling - reduces interrupt overhead in real-time DSP systems. |
| Auto-scan mode (2/3/4 inputs) | Automatically cycles through selected channels without software intervention - ideal for multi-sensor monitoring in automotive ECUs and industrial PLCs. |
| Glueless DSP interface | Direct connection to TI C5000/C6000 DSPs via parallel bus with no external logic - accelerates time-to-prototype for high-speed data acquisition subsystems. |
| 3-V/5-V digital interface compatible | Accepts 3.3-V or 5-V logic levels on DVDD/BVDD - enables interoperability with legacy 5-V controllers and modern low-voltage FPGAs without level shifters. |
Applications
| Radar Signal Acquisition | Automotive Powertrain Control |
|---|---|
Use Scenario: Digitizing I/Q baseband outputs from RF receivers in 77-GHz automotive radar modules. IC Role / Device Role / Timing Role: Simultaneous sampling of two differential IF channels with sub-ns aperture jitter to preserve phase coherence between antenna elements. Use Value: 68 dB SNR and 67 dB SFDR at 2 MHz enable detection of weak targets amid clutter; –40°C to 125°C rating ensures operation in engine bay environments. |
Use Scenario: Real-time sampling of cylinder pressure, camshaft position, and exhaust gas oxygen signals in gasoline direct injection engines. IC Role / Device Role / Timing Role: Four-channel synchronized acquisition with auto-scan mode to cycle through sensor inputs at variable engine speeds. Use Value: ±1 LSB DNL and internal 2.5-V reference ensure consistent combustion event timing accuracy across temperature extremes and vehicle lifetime. |
| Industrial Motor Drive Feedback | Communications Baseband Processing |
Use Scenario: Capturing three-phase current and DC-link voltage in servo inverters for field-oriented control (FOC). IC Role / Device Role / Timing Role: Simultaneous sampling of three single-ended current shunt signals plus one differential voltage channel to eliminate cross-channel timing errors. Use Value: 6 MSPS throughput and 54 MHz full-power bandwidth support 20-kHz PWM switching harmonics; TSSOP-32 footprint eases thermal management in compact drives. |
Use Scenario: Front-end digitization of analog IF signals in software-defined radio (SDR) transceivers for LTE/WiMAX base stations. IC Role / Device Role / Timing Role: Dual differential input configuration with 96 MHz small-signal bandwidth captures wide instantaneous bandwidths without aliasing. Use Value: 65 dB SINAD and 71 dB SFDR meet 3GPP adjacent channel leakage ratio (ACLR) requirements; integrated FIFO decouples ADC timing from FPGA processing latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed simultaneous-sampling ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS8588SIPM | 16-bit, 1 MSPS, SAR architecture; no internal FIFO; SPI interface only; 100 kSPS typical throughput per channel in 8-channel mode. | Better dc accuracy and lower power, but lacks simultaneous 4-channel sampling and parallel interface - suited for precision data loggers, not real-time control loops. | Select when absolute accuracy >12-bit and power <100 mW are prioritized over speed and channel synchronization. |
| THS12082IDAR | Same 12-bit pipeline architecture; 8-channel input mux; 6 MSPS max; identical TSSOP-32 package and pinout except extended analog input count. | Supports 8 analog inputs with programmable channel selection - adds flexibility for multi-sensor systems but requires updated layout for AINx pin routing. | Choose when future scalability to >4 channels is required; drop-in replacement for THS1206QDAR with minimal firmware changes. |
Compared with ADS8588SIPM and THS12082IDAR, the THS1206QDAR uniquely balances 6 MSPS simultaneous 4-channel sampling, integrated FIFO, parallel interface, and automotive temperature range - making it optimal for time-critical embedded control where phase alignment and deterministic latency are non-negotiable.
Availability
THS1206QDAR is available at Aetrix Electronics and suitable for automotive radar modules, industrial motor drives, and communications baseband subsystems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for THS1206QDAR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance signal chain solutions, with decades of expertise in precision data converters and automotive-qualified ICs.
The THS1206 product line was designed for high-speed, multi-channel data acquisition in demanding real-time systems - particularly targeting radar, motor control, and communications infrastructure where simultaneous sampling, low latency, and ruggedized operation are essential.
FAQ
What is the guaranteed operating temperature range for THS1206QDAR?
The THS1206QDAR is characterized and tested for continuous operation from –40°C to +125°C, meeting automotive-grade environmental requirements. This specification is validated per the THS1206Q device grade and applies specifically to the THS1206QDAR variant in TSSOP-32 packaging.
Does THS1206QDAR support differential input configurations?
Yes, THS1206QDAR supports differential input configurations using AINP/AINM and BINP/BINM pin pairs. Each pair can be independently configured as differential, enabling simultaneous sampling of two fully differential channels with 96 MHz small-signal bandwidth and –70 dB THD performance.
How does the internal FIFO in THS1206QDAR reduce host processor load?
The THS1206QDAR's 16-word deep FIFO buffers converted data, allowing the host processor to read batches instead of individual samples. The DATA_AV signal indicates FIFO occupancy level, enabling efficient interrupt-driven reads or polled access - reducing CPU overhead by up to 70% compared to direct register-read architectures.
Can THS1206QDAR operate with an external reference voltage?
Yes, THS1206QDAR supports external reference voltages applied to REFP and REFM pins. When configured via control register 0, the external reference overrides the internal 3.5 V/1.5 V pair, enabling custom full-scale ranges and improved dc accuracy for metrology-grade applications.
Is THS1206QDAR pin-compatible with any other Texas Instruments ADCs?
Yes, THS1206QDAR is pin-compatible with the THS10064 in TSSOP-32 packaging. However, THS10064 is a 10-bit, 6 MSPS device without FIFO or auto-scan mode. Migration to THS1206QDAR requires firmware updates to leverage 12-bit resolution and enhanced features but retains identical PCB layout.
THS1206QDAR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 6M
- Number of Inputs:
- 2, 4
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-MUX-ADC
- Ratio - S/H:ADC:
- 4:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 5V
- Voltage - Supply, Digital:
- 3V ~ 5.25V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 125°C
- Supplier Device Package:
- 32-TSSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
THS1206QDAR FAQ
1.How can I place an order for THS1206QDAR through Aetrix?
Please submit a Request for Quotation (RFQ) for THS1206QDAR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for THS1206QDAR reliable?
The price and inventory of THS1206QDAR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for THS1206QDAR is usually 5 days.
3.What payment methods are accepted for THS1206QDAR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for THS1206QDAR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for THS1206QDAR?
THS1206QDAR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your THS1206QDAR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for THS1206QDAR?
For technical support, including THS1206QDAR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your THS1206QDAR requirements.
6.How does Aetrix verify that THS1206QDAR is sourced from the original manufacturer or authorized distributors?
All THS1206QDAR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that THS1206QDAR meets industry standards.
7.What is the process for return or replacement of THS1206QDAR?
All THS1206QDAR units undergo pre-shipment inspection (PSI). If there is an issue with THS1206QDAR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The THS1206QDAR part is unused and in its original packaging.
Return procedure for THS1206QDAR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
THS1206QDAR Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

