Texas Instruments THS3062DR
- Part No.:
- THS3062DR
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
THS3062DR.pdf
- Description:
- IC OPAMP CFA 2 CIRCUIT 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,560
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
THS3062DR from Texas Instruments is a dual-channel, high-voltage, current-feedback amplifier optimized for low-distortion, high-slew-rate signal conditioning in video, VDSL, and high-speed ADC driver applications. It delivers 7000 V/μs slew rate (±15 V), 300 MHz unity-gain bandwidth, –81 dBc 3rd-harmonic distortion at 10 MHz (G = 2, RL = 150 Ω), ±145 mA output drive into 50 Ω, and operates from ±5 V to ±15 V supplies.
For engineers reviewing the THS3062DR datasheet, THS3062DR pinout, THS3062DR application, or THS3062DR equivalent, key selection criteria include its current-feedback architecture enabling stable high-gain bandwidth scaling, PowerPAD-enhanced thermal performance in SOIC-8 and MSOP-8 packages, and verified differential gain/phase performance for NTSC/PAL video line driving.
Technical Context
The THS3062DR implements a true current-feedback topology with separate high-impedance noninverting input and low-impedance inverting input, enabling bandwidth to be set primarily by feedback resistor value rather than closed-loop gain. Its BiCOM-I process supports ±15 V operation while maintaining 2.6 nV/√Hz input voltage noise and <0.3 dB peaking in unity-gain configuration.
Bandwidth scales inversely with feedback resistance: 220 MHz at G = 10 (Rf = 200 Ω), 275 MHz at G = 2 (Rf = 560 Ω), and 300 MHz at G = 1 (Rf = 750 Ω). Slew rate remains constant across output step size up to 20 V under ±15 V supply, with 1 ns rise/fall time and 30 ns 0.1% settling time for 2-V steps.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Unity-Gain Bandwidth | 300 MHz - Enables stable wideband amplification without phase-margin collapse at G = 1. |
| Slew Rate | 7000 V/μs - Supports full-scale 10-V output transitions in ≤1.4 ns, critical for pulse fidelity in test equipment. |
| 3rd-Harmonic Distortion | –81 dBc @ 10 MHz, G = 2, RL = 150 Ω - Meets broadcast video line-driver spectral purity requirements. |
| Output Current Drive | ±145 mA into 50 Ω - Directly drives twisted-pair telecom lines or back-terminated video loads without external buffers. |
| Supply Voltage Range | ±5 V to ±15 V - Compatible with legacy industrial ±12 V and high-dynamic-range ±15 V systems. |
| Input Voltage Noise | 2.6 nV/√Hz - Low enough to preserve SNR in high-gain preamplifier stages before 14-bit+ ADCs. |
| Differential Phase/Gain | 0.01° / 0.02% @ NTSC/PAL - Validated for composite video transmission without color shift or luminance error. |
Pinout & Package
THS3062DR is available in SOIC-8 (D) and MSOP-8 PowerPAD (DGN) packages. Both variants feature thermally enhanced underside copper pads requiring PCB thermal plane connection per TI SLMA002 guidelines. The SOIC-8 PowerPAD variant (DDA) offers lowest θJC (9.2°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1VOUT | Channel 1 output | Low-impedance current-output node; requires direct routing to load or termination to avoid instability. |
| 1VIN− | Channel 1 inverting input | Low-impedance (71 Ω) current-summing node; sets closed-loop gain via Rf to VOUT. |
| 1VIN+ | Channel 1 noninverting input | High-impedance (518 kΩ) voltage-input node; referenced to system ground or common-mode bias. |
| VS− | Negative supply rail | Must be decoupled with ≥0.1 µF ceramic + 10 µF tantalum near package; shared between both channels. |
| VS+ | Positive supply rail | Must be decoupled identically to VS−; total supply current is 2 × quiescent (max 12 mA/channel @ ±15 V). |
| 2VOUT | Channel 2 output | Independent output stage; electrically isolated from Channel 1 except via shared supply rails. |
| 2VIN− | Channel 2 inverting input | Identical electrical characteristics to 1VIN−; enables dual independent current-feedback paths. |
| 2VIN+ | Channel 2 noninverting input | Identical to 1VIN+; allows fully differential or single-ended dual-channel configurations. |
Key Features
| Feature | Design Value |
|---|---|
| Current-feedback architecture | Enables bandwidth scaling with gain: 220 MHz at G = 10 vs. 300 MHz at G = 1, unlike voltage-feedback op-amps. |
| PowerPAD thermal enhancement | Reduces junction-to-case thermal resistance to 9.2°C/W (DDA) - essential for sustained ±145 mA output into 50 Ω. |
| Low distortion at high frequency | –81 dBc HD3 @ 10 MHz ensures clean spectral content in VDSL upstream band (up to 12 MHz) and video baseband. |
| High output current capability | ±145 mA sourcing/sinking eliminates need for external buffer stages in line-driver applications. |
| Wide supply range support | Operates from ±4.5 V to ±16.5 V absolute max - accommodates both low-power portable and high-dynamic-range instrumentation. |
Applications
| Video Line Driver | VDSL Line Driver |
|---|---|
|
Use Scenario: Driving 75-Ω coaxial cable in broadcast-quality SD/HD video distribution systems with NTSC/PAL compliance. IC Role / Device Role / Timing Role: Final-stage buffer amplifier providing differential drive, DC-coupled level shifting, and impedance matching. Use Value: 0.01° differential phase error preserves color fidelity; ±145 mA drive sustains 2-VPP signal over 300-m cable runs. |
Use Scenario: Transmitting upstream signals (up to 12 MHz) over twisted-pair telephone lines in VDSL2 CPE equipment. IC Role / Device Role / Timing Role: High-linearity transmit driver with programmable common-mode bias for ADSL/VDSL line interface units (LIUs). Use Value: –81 dBc HD3 at 10 MHz meets ITU-T G.993.2 spectral mask; ±15 V operation supports >20 dBm line power. |
| High-Voltage ADC Preamplifier | Test & Measurement Signal Generator |
|
Use Scenario: Conditioning sensor outputs (e.g., piezoelectric, strain gauge) prior to 14-bit+ SAR or pipeline ADCs. IC Role / Device Role / Timing Role: Gain-setting, anti-aliasing filter driver, and level-shifting stage with rail-to-rail output swing. Use Value: 2.6 nV/√Hz input noise contributes <0.5 LSB error in 16-bit 1-MSPS systems; 120 MHz large-signal BW supports fast step response. |
Use Scenario: Output stage of arbitrary waveform generators (AWGs) and high-speed digital pattern generators requiring sub-ns edge fidelity. IC Role / Device Role / Timing Role: Final output buffer delivering programmable amplitude, offset, and impedance-matched waveforms. Use Value: 7000 V/μs slew rate enables <1.5 ns 10–90% rise time on 10-V steps; 30 ns 0.1% settling ensures accurate multi-level pulse generation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed current-feedback amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| THS3092DR | Higher slew rate (8500 V/μs), lower distortion (–87 dBc HD3 @ 10 MHz), but higher quiescent current (13.5 mA/channel). | Better suited for repetitive sine-wave applications >900 V/μs where THS3062DR is not recommended per TI documentation. | Select THS3092DR when driving continuous high-frequency sinusoids or demanding RF IF stages; THS3062DR remains optimal for pulsed/line-driver use. |
| OPA691IDR | Lower slew rate (5500 V/μs), wider supply range (±5 V to ±6 V single-supply compatible), 350 mA output drive, but reduced bandwidth (280 MHz G = 1). | Preferred for low-voltage, high-current applications like portable ultrasound transducer drivers or battery-powered test gear. | Choose OPA691IDR when 350 mA sink/source into 25 Ω is required and ±15 V operation is unnecessary; THS3062DR excels in ±15 V, low-distortion video/VDSL roles. |
Compared with THS3062DR, THS3092DR provides superior harmonic suppression for continuous-wave signals but consumes more power, while OPA691IDR trades bandwidth and voltage range for extreme output current-making THS3062DR the balanced choice for ±15 V, low-distortion, dual-channel line driving.
Availability
THS3062DR is available at Aetrix Electronics and suitable for video line driving, VDSL line interface, and high-speed ADC preamplifier applications requiring stable component supply, long-term industrial lifecycle support, and traceable sourcing from authorized channels.
Supply support for THS3062DR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-performance amplifier design and manufacturing.
The THS3062DR belongs to TI's high-speed current-feedback amplifier product line, engineered specifically for applications demanding simultaneous high slew rate, wide bandwidth, low distortion, and robust output drive-such as professional video infrastructure and broadband communications equipment.
FAQ
What is the maximum safe operating voltage for THS3062DR?
The THS3062DR has an absolute maximum supply voltage rating of ±16.5 V per the datasheet Absolute Maximum Ratings table. Continuous operation is specified from ±5 V to ±15 V, with thermal limits dictating practical upper bounds-especially in SOIC-8 (D) packages where power dissipation must stay below 410 mW at +85°C ambient. Exceeding ±16.5 V risks permanent damage.
Does THS3062DR support single-supply operation?
THS3062DR is explicitly designed for dual-supply operation (±5 V to ±15 V) and does not support true single-supply use. Its input common-mode range is limited to ±13.1 V at ±15 V supplies and ±3.1 V at ±5 V supplies-centered around ground-not the positive rail. For single-supply applications, TI recommends alternatives like OPA691 or THS3202 that specify rail-to-rail input/output and single-supply bias schemes.
How does THS3062DR's current-feedback architecture affect stability in gain-of-10 configurations?
In gain-of-10 configurations, THS3062DR requires Rf = 200 Ω (per Table 1 in the datasheet) to maintain 220 MHz bandwidth and adequate phase margin. Using higher Rf values causes bandwidth collapse and potential peaking or oscillation. Stability is ensured by adhering to TI-recommended feedback/gain resistor pairs and using 1% tolerance metal-film resistors placed close to the inverting input pins.
Can THS3062DR drive a 150-Ω load while maintaining NTSC video specifications?
Yes-THS3062DR is characterized for differential gain of 0.02% and differential phase of 0.01° into 150-Ω loads at NTSC frequencies, meeting broadcast video standards. This performance holds at G = 2, ±15 V supply, and Rf = 560 Ω. Load matching and proper termination are essential; the device's ±145 mA output ensures headroom even with multiple parallel 150-Ω loads.
What thermal considerations apply to THS3062DR in SOIC-8 PowerPAD (DDA) packaging?
The THS3062DR in SOIC-8 PowerPAD (DDA) package achieves θJC = 9.2°C/W, requiring connection of the exposed thermal pad to a dedicated PCB copper plane for effective heat transfer. Without this, junction temperature can exceed +125°C under full ±145 mA load, triggering thermal shutdown or accelerated aging. TI technical brief SLMA002 details minimum pad size, via count, and copper area requirements.
THS3062DR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Amplifier Type:
- Current Feedback
- Number of Circuits:
- 2
- Output Type:
- -
- Slew Rate:
- 7000V/µs
- Gain Bandwidth Product:
- 2.2 GHz
- -3db Bandwidth:
- 300 MHz
- Current - Input Bias:
- 6 µA
- Voltage - Input Offset:
- 700 µV
- Current - Supply:
- 8.3mA
- Current - Output / Channel:
- 145 mA
- Voltage - Supply Span (Min):
- 10 V
- Voltage - Supply Span (Max):
- 30 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
THS3062DR FAQ
1.How can I place an order for THS3062DR through Aetrix?
Please submit a Request for Quotation (RFQ) for THS3062DR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for THS3062DR reliable?
The price and inventory of THS3062DR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for THS3062DR is usually 5 days.
3.What payment methods are accepted for THS3062DR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for THS3062DR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for THS3062DR?
THS3062DR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your THS3062DR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for THS3062DR?
For technical support, including THS3062DR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your THS3062DR requirements.
6.How does Aetrix verify that THS3062DR is sourced from the original manufacturer or authorized distributors?
All THS3062DR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that THS3062DR meets industry standards.
7.What is the process for return or replacement of THS3062DR?
All THS3062DR units undergo pre-shipment inspection (PSI). If there is an issue with THS3062DR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The THS3062DR part is unused and in its original packaging.
Return procedure for THS3062DR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
THS3062DR Tags

-
LM358DT
STMicroelectronics

-
LM358DR
Texas Instruments

-
LM2904DR
Texas Instruments

-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments

-
MCP6006T-E/OT
Microchip Technology

-
MCP6006UT-E/OT
Microchip Technology

-
LM324PWR
Texas Instruments

-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments

-
LM358P
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
