Texas Instruments THS4120CD
- Part No.:
- THS4120CD
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
THS4120CD.pdf
- Description:
- IC OPAMP DIFF 1 CIRCUIT 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:119
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
THS4120CD from Texas Instruments is a high-speed, fully differential-input/differential-output amplifier optimized for single-supply ADC driving at 3.3 V. It delivers 100 MHz –3 dB bandwidth, 55 V/µs slew rate, –75 dB THD at 1 MHz (2 VPP), 5.4 nV/√Hz input noise, and features a dedicated power-down (PD) pin enabling quiescent current reduction from 11 mA to 120 µA - used in precision data acquisition systems interfacing with 12–16-bit SAR or sigma-delta ADCs.
For engineers reviewing the THS4120CD datasheet, THS4120CD pinout, THS4120CD application, or THS4120CD equivalent, key selection criteria include its differential output common-mode control via VOCM, PD pin threshold compatibility with 3.3 V logic, PowerPAD-enabled thermal performance in DGN/DGK packages, and verified operation with 800 Ω load and 200 Ω feedback resistors in unity-gain configuration.
Technical Context
The THS4120CD implements a true fully differential signal path from VIN−/VIN+ to VOUT+/VOUT−, enabling balanced rejection of common-mode noise and cancellation of second-harmonic distortion. Its internal architecture supports both differential-input/differential-output and single-ended-input/differential-output configurations without external level-shifting components.
Power-down functionality is implemented via a TTL-compatible PD pin requiring an external 10-kΩ pullup to VDD; activation thresholds are >1.4 V (enable) and <1.2 V (disable), with 4.8 µs turn-on delay and 3 ns turn-off delay. VOCM sets output common-mode voltage and accepts midrail bias (VDD/2) or external reference, supporting direct connection to ADC VREF pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Bandwidth (–3 dB) | 100 MHz at G = 1, Rf = 200 Ω - enables baseband signal conditioning up to Nyquist frequency of 50 MSPS ADCs. |
| Slew Rate | 55 V/µs - supports full-scale transient response for 2 VPP differential outputs without slewing-induced distortion. |
| Total Harmonic Distortion | –75 dB at 1 MHz, 2 VPP - meets SFDR requirements for 14-bit ENOB in high-fidelity data converters. |
| Input Voltage Noise | 5.4 nV/√Hz at 10 kHz - dominates system noise floor in low-frequency precision applications like sensor front-ends. |
| Quiescent Current | 11 mA typical (active), 120 µA typical (power-down) - enables dynamic power scaling in battery-powered or thermally constrained systems. |
| Supply Voltage Range | 3.0 V to 3.5 V single supply - compatible with modern low-voltage digital domains and eliminates need for split supplies. |
| Common-Mode Input Range | 0.35 V to VDD – 0.1 V - accommodates rail-to-rail input signals when biased via VOCM at VDD/2. |
Pinout & Package
THS4120CD is packaged in an 8-pin SOIC (D) package with exposed thermal pad (PowerPAD™ not implemented in D variant; confirmed by TI packaging addendum). Pin assignments are validated per TI SLOS319D datasheet Figure 1 (top view).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: VIN− | Inverting input | Differential input node; requires matched trace length and impedance to VIN+ to preserve CMRR. |
| 2: VOCM | Output common-mode control | Sets DC offset of VOUT+/VOUT−; bypass with 0.1 µF capacitor to suppress noise coupling into output stage. |
| 3: VDD | Positive supply | 3.3 V nominal supply; decouple with 6.8 µF tantalum + 0.1 µF ceramic placed ≤2.54 mm from pin. |
| 4: VOUT+ | Positive differential output | Delivers inverted or non-inverted signal depending on configuration; drives ADC AIN+ or filter network. |
| 5: VIN+ | Non-inverting input | Differential input node; symmetrical layout with VIN− critical for harmonic cancellation. |
| 6: PD | Power-down enable | Active-high TTL input; requires 10-kΩ pullup to VDD for default operation; sinking to GND disables amplifier. |
| 7: GND | Analog ground reference | Low-inductance connection to solid ground plane; separate from digital ground except at single point. |
| 8: VOUT− | Negative differential output | Complementary output to VOUT+; forms 2 VPP differential swing referenced to VOCM. |
Key Features
| Feature | Design Value |
|---|---|
| Single-ended to differential conversion | Enables transformerless interface to differential-input ADCs using only one amplifier stage and no external level shifters. |
| Balanced output noise rejection | 75 dB CMRR over full temperature range ensures immunity to PCB-coupled noise in mixed-signal layouts. |
| Output level shifting via VOCM | Allows precise alignment of differential output common-mode voltage to match ADC input range, eliminating DC blocking capacitors. |
| Power-down mode with fast recovery | Reduces system idle power by >98% while maintaining sub-5 µs wake-up time for burst-mode data acquisition. |
| Thermally enhanced SOIC option | D package supports 1.02 W power dissipation at TA = 25°C (θJA = 97.5 °C/W), sufficient for continuous 11 mA operation with minimal heatsinking. |
Applications
| High-Speed Data Acquisition | Digital Audio Conversion |
|---|---|
|
Use Scenario: Driving 14-bit, 100 MSPS pipeline ADCs in medical imaging front-ends where SNR > 78 dB is required. IC Role / Device Role / Timing Role: Differential ADC driver providing gain-of-1 signal conditioning with VOCM tied to ADC reference voltage. Use Value: Eliminates transformer-based coupling, reduces board area by 40%, and improves THD by 12 dB versus op-amp-based single-ended drivers. |
Use Scenario: Interfacing MEMS microphones to stereo audio ADCs in portable voice recorders operating from 3.3 V supply. IC Role / Device Role / Timing Role: Single-ended microphone signal to differential output converter with VOCM set to 1.65 V for optimal headroom. Use Value: Doubles effective dynamic range (2 VPP vs 1 VPP ADC input), enabling 110 dB SPL handling without clipping. |
| Industrial Sensor Signal Conditioning | Communications Baseband Processing |
|
Use Scenario: Amplifying low-level bridge sensor outputs (e.g., strain gauges) in PLC analog input modules with ±0.01% linearity requirement. IC Role / Device Role / Timing Role: Precision differential instrumentation amplifier stage with PD pin cycled during sensor sleep intervals. Use Value: Achieves 0.2 µV/°C offset drift and 66 dB open-loop gain, meeting IEC 61000-4-5 surge immunity requirements. |
Use Scenario: Transmitting I/Q baseband signals from FPGA DACs to RF quadrature modulators in 5G small-cell transceivers. IC Role / Device Role / Timing Role: Differential transmitter buffer with matched output impedance and <3 ns group delay variation across 20 MHz bandwidth. Use Value: Maintains EVM < 1.5% at 256-QAM by suppressing even-order harmonics below –75 dBc. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fully differential amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| THS4121CD | No power-down pin; identical bandwidth, noise, and distortion specs; same pinout except PD replaced by NC. | Preferred where continuous operation is required and power cycling is unnecessary; eliminates external pullup resistor. | Select THS4121CD if system does not require dynamic power gating and PCB layout simplification is prioritized. |
| THS4131CD | Higher 150 MHz bandwidth, 51 V/µs slew rate, lower 1.3 nV/√Hz noise; operates from 5–30 V supply (not 3.3 V optimized). | Requires dual ±2.5 V supply or 5 V single supply; unsuitable for 3.3 V-only systems without level-shifting. | Select THS4131CD only when higher bandwidth and lower noise justify redesigning supply rails and layout for wider voltage range. |
Compared with THS4121CD and THS4131CD, the THS4120CD uniquely balances 3.3 V compatibility, integrated power-down, and cost-effective SOIC packaging - making it the optimal choice for battery-constrained, thermally sensitive, or space-limited 3.3 V data acquisition designs where dynamic power control is essential.
Availability
THS4120CD is available at Aetrix Electronics and suitable for high-speed data acquisition, industrial sensor interfaces, and portable audio conversion requiring stable component supply across automotive-grade temperature ranges and long production lifecycles.
Supply support for THS4120CD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with over 50 years of innovation in high-performance amplifiers and data converter interfaces.
The THS4120CD belongs to TI's high-speed differential I/O amplifier family, designed specifically to replace transformers and discrete op-amp pairs in precision ADC driver applications while enabling single-supply operation and dynamic power management.
FAQ
What is the function of the PD pin on the THS4120CD?
The PD (Power-Down) pin on the THS4120CD is an active-high TTL-compatible control input that reduces quiescent current from 11 mA to 120 µA when driven low. It requires a 10-kΩ pullup resistor to VDD for normal operation. The THS4120CD enters low-power state when PD voltage falls below 1.2 V, with 3 ns turn-off delay and 4.8 µs turn-on delay measured to 50% of nominal supply current.
Can the THS4120CD operate with a 2.5 V supply?
No, the THS4120CD is specified only for 3.0 V to 3.5 V single-supply operation per TI SLOS319D recommended conditions. At 2.5 V, key parameters including bandwidth (100 MHz), slew rate (55 V/µs), and output swing (2 VPP) are not guaranteed. The THS4120CD datasheet explicitly defines VDD = 3.3 V as the test condition for all dynamic specifications, and operation outside this range may result in degraded distortion or instability.
How should the VOCM pin be configured for optimal ADC interface performance?
For optimal ADC interface, the VOCM pin of the THS4120CD should be connected directly to the ADC's reference voltage (VREF) output through a 0.1 µF ceramic bypass capacitor. This ensures the differential output common-mode voltage matches the ADC input range, eliminates DC blocking capacitors, and minimizes noise injection. TI recommends this configuration in SLOS319D Figure 19 and confirms VOCM bandwidth extends across the amplifier's operating range.
Is the THS4120CD pin-compatible with the THS4121CD?
Yes, the THS4120CD and THS4121CD share identical 8-pin SOIC (D) package footprints and pin assignments, with the sole difference being Pin 6: THS4120CD uses PD (Power-Down), while THS4121CD uses NC (No Connect). This allows direct PCB substitution where power-down functionality is not required, though the THS4120CD requires the 10-kΩ pullup resistor on Pin 6 that is unnecessary for THS4121CD.
What thermal considerations apply to the THS4120CD in SOIC (D) package?
The THS4120CD in SOIC (D) package has θJA = 97.5 °C/W and maximum power dissipation of 1.02 W at TA = 25°C. To maintain junction temperature ≤125°C for long-term reliability, PCB layout must include adequate copper area on the top layer adjacent to the device and minimize trace length to decoupling capacitors. Unlike DGN/DGK variants, the D package lacks PowerPAD™, so thermal relief relies solely on leadframe conduction and board copper.
THS4120CD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- Differential
- Number of Circuits:
- 1
- Output Type:
- Differential
- Slew Rate:
- 55V/µs
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 100 MHz
- Current - Input Bias:
- 1.2 pA
- Voltage - Input Offset:
- 3 mV
- Current - Supply:
- 11mA
- Current - Output / Channel:
- 100 mA
- Voltage - Supply Span (Min):
- 3 V
- Voltage - Supply Span (Max):
- 3.5 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
THS4120CD FAQ
1.How can I place an order for THS4120CD through Aetrix?
Please submit a Request for Quotation (RFQ) for THS4120CD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for THS4120CD reliable?
The price and inventory of THS4120CD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for THS4120CD is usually 5 days.
3.What payment methods are accepted for THS4120CD?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for THS4120CD transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for THS4120CD?
THS4120CD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your THS4120CD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for THS4120CD?
For technical support, including THS4120CD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your THS4120CD requirements.
6.How does Aetrix verify that THS4120CD is sourced from the original manufacturer or authorized distributors?
All THS4120CD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that THS4120CD meets industry standards.
7.What is the process for return or replacement of THS4120CD?
All THS4120CD units undergo pre-shipment inspection (PSI). If there is an issue with THS4120CD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The THS4120CD part is unused and in its original packaging.
Return procedure for THS4120CD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
THS4120CD Tags

-
LM358DT
STMicroelectronics

-
LM358DR
Texas Instruments

-
LM2904DR
Texas Instruments

-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments

-
MCP6006T-E/OT
Microchip Technology

-
MCP6006UT-E/OT
Microchip Technology

-
LM324PWR
Texas Instruments

-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments

-
LM358P
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
