Texas Instruments THS4130CD
- Part No.:
- THS4130CD
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
THS4130CD.pdf
- Description:
- IC OPAMP DIFF 1 CIRCUIT 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,393
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Product details
Overview
THS4130CD from Texas Instruments is a fully differential input/output amplifier optimized for high-speed, low-noise signal conditioning in precision analog front-ends. It delivers 170 MHz small-signal bandwidth, –102 dBc THD at 250 kHz (±15 V supply), and 1.25 nV/√Hz input voltage noise, enabling high-fidelity differential ADC driving and single-ended-to-differential conversion in medical ultrasound and test equipment.
For engineers reviewing the THS4130CD datasheet, THS4130CD pinout, THS4130CD application, or THS4130CD equivalent, this page provides verified specifications, SOIC-8 package details, power-down functionality, common-mode rejection behavior, and validated alternative options for differential signal chain design.
Technical Context
The THS4130CD implements a true fully differential architecture with matched internal gain stages and a dedicated VOCM input that directly sets output common-mode voltage. Its complementary bipolar process enables ±15 V dual-supply operation and 95 dB CMRR at 800 kHz, supporting robust noise rejection in mixed-signal systems.
It features an active-low power-down pin (Pin 7) that reduces quiescent current to 860 µA while placing outputs in high-impedance state (>1 MΩ). The device operates across –40°C to +85°C and supports both single-ended and differential input configurations via external resistor networks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Small-signal bandwidth | 170 MHz at ±15 V supply - enables wideband signal acquisition up to ~100 MHz usable baseband. |
| Slew rate | 51 V/µs - supports fast transient response for 2 VPP signals without distortion. |
| Total harmonic distortion | –102 dBc at 250 kHz, 2 VPP, ±15 V - ensures minimal spectral contamination in precision digitization. |
| Input voltage noise | 1.25 nV/√Hz at 10 kHz - critical for preserving SNR in low-amplitude sensor interfaces. |
| Common-mode rejection | 95 dB at 800 kHz - suppresses coupled interference in noisy industrial or medical environments. |
| Supply range | ±2.5 V to ±15 V (dual) or 5 V to 30 V (single) - accommodates legacy ±15 V rails and modern low-voltage systems. |
| Quiescent current (shutdown) | 860 µA - enables power-gating in battery-sensitive portable instrumentation. |
Pinout & Package
THS4130CD is packaged in an 8-pin SOIC (D package), with exposed thermal pad not present - unlike HVSSOP variants. Pin functions are electrically defined and validated per TI SLOS318L (Rev L, Aug 2023).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN+ | Differential input (+) | High-impedance node accepting single-ended or differential input; requires matched layout to VIN–. |
| PD | Power-down control | Active-low logic input; pulled high internally to VCC+ via 250 kΩ; drives amplifier into high-Z shutdown below 1.4 V above VCC–. |
| VCC– | Negative supply rail | Connects to negative supply; also reference for PD threshold and VOCM mid-rail calculation. |
| VOUT– | Differential output (–) | Complementary output; must be terminated symmetrically with VOUT+ for optimal balance and CMRR. |
| VIN– | Differential input (–) | Matched counterpart to VIN+; imbalance degrades output balance error and HD2 performance. |
| VOCM | Output common-mode setpoint | Low-impedance input setting DC offset of differential outputs; bypass with 0.1 µF to minimize noise coupling. |
| VCC+ | Positive supply rail | Connects to positive supply; powers internal bias circuitry and output stage; source for internal PD pull-up. |
| VOUT+ | Differential output (+) | Primary output node; differential swing limited to ±11.2 V (±15 V supply, full temp range) into 1 kΩ. |
Key Features
| Feature | Design Value |
|---|---|
| Fully differential I/O architecture | Eliminates need for external baluns or transformer coupling; enables direct interface to differential ADCs like AFE58JD18. |
| 95 dB CMRR at 800 kHz | Rejects board-level EMI and ground bounce in high-density mixed-signal PCBs without additional filtering. |
| 1.25 nV/√Hz input voltage noise | Maintains >90 dB SNR for 16-bit ADCs sampling at 1 MSPS when driving 50 Ω–200 Ω loads. |
| Active-low power-down (PD) | Reduces system standby power by >90% while preserving signal path integrity during sleep cycles. |
| VOCM-controlled output offset | Allows precise alignment of differential output to ADC input common-mode range (e.g., 2.5 V for 5 V supplies). |
Applications
| Medical Ultrasound Beamforming | Differential ADC Driver |
|---|---|
Use Scenario: Time-gain control (TGC) amplification stage feeding AFE58JD18 ultrasound receiver channel. IC Role / Device Role / Timing Role: Single-ended DAC output level-shifting and conversion to high-SNR differential signal for ADC sampling. Use Value: 1.25 nV/√Hz noise floor preserves weak echo signal fidelity; –102 dBc THD prevents harmonic artifacts masking tissue boundaries. |
Use Scenario: Driving THS1206 or similar 12-bit differential SAR ADC in automated test equipment. IC Role / Device Role / Timing Role: Final gain stage and common-mode level translator before ADC input pins. Use Value: 170 MHz bandwidth supports >50 MSPS sampling; VOCM pin enables exact matching to ADC's 2.048 V reference midpoint. |
| Single-Ended to Differential Conversion | Digital-to-Analog Converter Output Buffer |
Use Scenario: Interfacing DAC8802 (CH_A/CH_B) to differential-input signal processing chain. IC Role / Device Role / Timing Role: Converts unipolar single-ended DAC output into balanced ±2 V differential signal with controlled common-mode. Use Value: Resistor-matched feedback network (390 Ω) achieves <0.1% output balance error; PD pin enables dynamic power gating between DAC updates. |
Use Scenario: Post-DAC buffering in programmable power supply control loop with isolated feedback. IC Role / Device Role / Timing Role: High-speed, low-drift output buffer isolating DAC from reactive load; VOCM sets output center point for downstream comparator. Use Value: ±15 V supply capability delivers ±12.4 V swing into 1 kΩ; 2 µV/°C offset drift maintains accuracy over industrial temperature range. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fully differential amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| THS4131CD | No power-down pin; identical AC performance and noise specs; same SOIC-8 footprint. | Not suitable where dynamic power gating is required; preferred for always-on, space-constrained designs. | Select THS4131CD only if shutdown functionality is unnecessary and PCB layout must avoid unused PD trace. |
| LMH6552MA/NOPB | Higher 1.9 GHz GBW but 2.3 nV/√Hz noise; no VOCM pin; fixed-gain configuration only. | Better for RF IF amplification; unsuitable for precision ADC driver or VOCM-adjustable systems. | Choose LMH6552MA/NOPB only for wideband gain blocks where noise and DC adjustability are secondary to speed. |
Compared with THS4130CD, THS4131CD removes power management at no AC performance cost, while LMH6552MA/NOPB trades noise and flexibility for raw bandwidth - making THS4130CD the optimal choice for precision, power-aware differential signal chains.
Availability
THS4130CD is available at Aetrix Electronics and suitable for medical imaging systems, automated test equipment, and industrial data acquisition requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for THS4130CD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in high-performance amplifier design and manufacturing.
The THS413x product line was engineered specifically for demanding differential signal conditioning in ultrasound, test instrumentation, and high-resolution data acquisition - emphasizing low noise, high CMRR, and flexible common-mode control.
FAQ
What is the maximum supply voltage for THS4130CD?
The THS4130CD supports dual-supply operation up to ±15 V (30 V total) and single-supply operation from 5 V to 30 V. Absolute maximum supply voltage is 33 V, but recommended operating conditions specify ±15 V max for reliable long-term performance and thermal stability in the SOIC-8 package.
Does THS4130CD require external compensation capacitors?
No, THS4130CD is internally compensated for unity-gain stability. However, for capacitive loads >10 pF, a 20 Ω series resistor must be added at each output (VOUT+ and VOUT–) to maintain phase margin and prevent ringing - as confirmed in Figure 9-1 of the official datasheet.
How does the VOCM pin affect THS4130CD output swing?
The VOCM pin sets the DC common-mode level of both VOUT+ and VOUT–. For example, with VOCM = 2.5 V and ±5 V supplies, the outputs swing symmetrically around 2.5 V (e.g., 0.9 V to 4.1 V). Exceeding the valid VICM range (–4 V to +4.5 V) or driving VOCM with high impedance degrades CMRR and increases distortion.
Can THS4130CD drive a 50 Ω load directly?
THS4130CD can deliver up to 85 mA output current (±15 V, full temp range), supporting short-term 50 Ω drive. However, sustained 50 Ω loading causes significant self-heating in SOIC-8; TI recommends using the HVSSOP-8 (DGN) variant with thermal pad for continuous 50 Ω operation - THS4130CD is rated for 7 Ω pulsed loads only.
What is the function of the PD pin on THS4130CD?
The PD (power-down) pin on THS4130CD is an active-low digital control input. Pulling it ≤1.4 V above VCC– disables the amplifier, reducing quiescent current to 860 µA and placing outputs in high-impedance state (>1 MΩ). An internal 250 kΩ pull-up to VCC+ keeps the device enabled if PD is left unconnected.
THS4130CD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Amplifier Type:
- Differential
- Number of Circuits:
- 1
- Output Type:
- Differential
- Slew Rate:
- 52V/µs
- Gain Bandwidth Product:
- 225 MHz
- -3db Bandwidth:
- 150 MHz
- Current - Input Bias:
- 2 µA
- Voltage - Input Offset:
- 200 µV
- Current - Supply:
- 14mA
- Current - Output / Channel:
- 85 mA
- Voltage - Supply Span (Min):
- 5 V
- Voltage - Supply Span (Max):
- 30 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
THS4130CD FAQ
1.How can I place an order for THS4130CD through Aetrix?
Please submit a Request for Quotation (RFQ) for THS4130CD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for THS4130CD reliable?
The price and inventory of THS4130CD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for THS4130CD is usually 5 days.
3.What payment methods are accepted for THS4130CD?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for THS4130CD transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for THS4130CD?
THS4130CD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your THS4130CD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for THS4130CD?
For technical support, including THS4130CD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your THS4130CD requirements.
6.How does Aetrix verify that THS4130CD is sourced from the original manufacturer or authorized distributors?
All THS4130CD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that THS4130CD meets industry standards.
7.What is the process for return or replacement of THS4130CD?
All THS4130CD units undergo pre-shipment inspection (PSI). If there is an issue with THS4130CD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The THS4130CD part is unused and in its original packaging.
Return procedure for THS4130CD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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