Texas Instruments THS4130CDGKR
- Part No.:
- THS4130CDGKR
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
THS4130CDGKR.pdf
- Description:
- IC OPAMP DIFF 1 CIRCUIT 8VSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
THS4130CDGKR from Texas Instruments is a fully differential amplifier (FDA) designed for high-fidelity signal conditioning in precision analog front-ends. It delivers 170 MHz small-signal bandwidth, 51 V/µs slew rate, and –102 dBc THD at 250 kHz with ±15 V supplies - enabling low-distortion differential ADC driving in medical ultrasound and instrumentation systems.
For engineers reviewing the THS4130CDGKR datasheet, THS4130CDGKR pinout, THS4130CDGKR application, or THS4130CDGKR equivalent, this page provides verified electrical specifications, validated VSSOP-8 pin functions, confirmed power-down behavior, and real-world design context for single-ended-to-differential conversion and antialiasing filter interfaces.
Technical Context
The THS4130CDGKR implements a true fully differential signal path from input to output using TI's high-voltage complementary bipolar process, supporting supply ranges from ±2.5 V to ±15 V (or 5 V to 30 V single-supply). Its internal VCM error amplifier actively regulates output common-mode voltage via the VOCM pin, enabling precise level shifting independent of gain configuration.
It features an active-low power-down pin (PD) that reduces quiescent current to 860 µA while placing outputs in high-impedance state (>1 MΩ), and achieves 95 dB CMRR at 800 kHz - critical for rejecting noise in mixed-signal data acquisition chains where differential signaling improves dynamic range and suppresses even-order harmonics.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Small-signal bandwidth | 170 MHz at ±15 V supply - supports wideband signal chains up to ~100 MHz usable bandwidth with 1 V/V gain. |
| Slew rate | 51 V/µs - enables clean reproduction of fast transient signals without slewing-induced distortion in high-speed data converters. |
| Total harmonic distortion | –102 dBc at 2 VPP, 250 kHz, ±15 V - ensures minimal spectral contamination in sensitive measurement and imaging applications. |
| Input voltage noise | 1.25 nV/√Hz at 10 kHz - contributes <1.8 µV RMS integrated noise over 100 kHz bandwidth, preserving SNR in low-level signal amplification. |
| Quiescent current (shutdown) | 0.86 mA - allows low-power standby mode in battery-sensitive or thermally constrained systems without disconnecting supplies. |
| Common-mode rejection ratio | 95 dB at 800 kHz - rejects coupled interference in noisy industrial or medical environments where ground loops are present. |
| Supply voltage range | ±2.5 V to ±15 V dual or 5 V to 30 V single - accommodates legacy ±15 V rails and modern low-voltage systems without external level-shifting circuitry. |
Pinout & Package
VSSOP-8 (DGK) package: 8-pin, 3.0 mm × 3.0 mm body, 0.65 mm pitch, exposed thermal pad (electrically isolated, recommended to connect to PCB ground plane for thermal performance).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN+ | Differential input (non-inverting) | Accepts positive half of fully differential or single-ended input; matched impedance required with VIN– for balance. |
| PD | Active-low power-down control | Pulled to VCC– to disable amplifier; internal 250 kΩ pull-up to VCC+ keeps device active if left unconnected. |
| VCC– | Negative supply rail | Supports dual-supply operation down to –15 V; must be decoupled with low-ESR capacitor near pin. |
| VOUT– | Differential output (inverted) | Provides complementary output signal; requires matched termination and layout symmetry vs VOUT+. |
| VIN– | Differential input (inverting) | Accepts negative half of differential input or reference node for single-ended configuration. |
| VOCM | Output common-mode voltage setpoint | DC voltage applied here defines midpoint of differential output swing; bypass with 0.1 µF capacitor to reduce noise coupling. |
| VCC+ | Positive supply rail | Supports dual-supply operation up to +15 V; decoupling essential for stability and PSRR performance. |
| VOUT+ | Differential output (non-inverted) | Primary output leg; combined with VOUT– forms true differential pair with 180° phase relationship and balanced amplitude. |
Key Features
| Feature | Design Value |
|---|---|
| Fully differential I/O architecture | Enables direct interface to differential ADCs and DACs without external baluns or transformers, reducing component count and board area. |
| Active VOCM pin control | Allows precise setting of output DC offset independent of gain, simplifying level-shifting in multi-stage signal chains with varying supply domains. |
| Power-down mode with high-Z outputs | Reduces system power by >90% while maintaining safe open-circuit state on outputs - critical for multiplexed or time-shared analog paths. |
| High CMRR (95 dB @ 800 kHz) | Maintains signal integrity in electrically noisy environments such as ultrasound transducer arrays or motor-drive feedback circuits. |
| Low 1/f noise corner (350 Hz) | Preserves accuracy in low-frequency measurements (e.g., ECG, sensor conditioning) where flicker noise dominates near DC. |
Applications
| Medical Ultrasound Imaging | Differential ADC Driver |
|---|---|
Use Scenario: Amplifying echo return signals from piezoelectric transducers before digitization in portable and cart-based ultrasound systems. IC Role / Device Role / Timing Role: Fully differential amplifier providing single-ended-to-differential conversion, gain, and common-mode level shifting for AFE58JD18 or similar ultrasound ADCs. Use Value: –102 dBc THD at 250 kHz and 170 MHz bandwidth preserve tissue contrast resolution and harmonic imaging fidelity across full imaging depth range. |
Use Scenario: Driving high-resolution SAR or pipeline ADCs (e.g., THS1206) in test equipment and data acquisition systems requiring >10-bit ENOB at >1 MSPS. IC Role / Device Role / Timing Role: Precision differential driver stage ensuring matched amplitude/phase response and minimized inter-symbol interference into ADC input pins. Use Value: 95 dB CMRR and 1.25 nV/√Hz input noise maintain effective number of bits (ENOB) under real-world PCB layout and supply noise conditions. |
| Single-Ended to Differential Conversion | Differential Antialiasing Filter Interface |
Use Scenario: Converting legacy single-ended sensor outputs (e.g., strain gauges, accelerometers) into differential format for noise-immune transmission over PCB traces or cables. IC Role / Device Role / Timing Role: Gain-stage FDA configured with single-ended input and differential output, referenced to VOCM for optimal ADC input range alignment. Use Value: Internal VCM error amplifier eliminates need for external op-amp bias networks, reducing BOM cost and layout complexity versus discrete solutions. |
Use Scenario: Buffering and driving passive or active antialiasing filters preceding high-speed ADCs in communication baseband receivers and spectrum analyzers. IC Role / Device Role / Timing Role: Low-output-impedance driver maintaining filter transfer function integrity despite capacitive loading and trace parasitics. Use Value: 51 V/µs slew rate and 170 MHz bandwidth ensure linear phase response through cutoff frequency, preventing passband ripple and group delay distortion. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fully differential amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| THS4131CDGKR | No power-down pin; 15.4 µA max input bias current vs 5 µA typical for THS4130CDGKR; identical bandwidth and noise specs. | Lacks shutdown capability - unsuitable for power-gated signal paths but offers slightly lower input current-induced offset drift. | Select THS4131CDGKR only when continuous operation is guaranteed and PD functionality is unnecessary. |
| LMH5401RTVT | Higher 1800 MHz GBW, 3.5 nV/√Hz noise, no VOCM pin; uses current-feedback architecture instead of voltage-feedback. | Better suited for >100 MSPS ADC drivers but requires different compensation and lacks flexible common-mode control. | Choose LMH5401RTVT for ultra-high-speed applications where VOCM flexibility is secondary to raw bandwidth and settling time. |
Compared with THS4130CDGKR, THS4131CDGKR removes power management at the cost of design flexibility, while LMH5401RTVT trades configurability and noise performance for extreme speed - making THS4130CDGKR the optimal choice for precision, power-aware differential signal conditioning below 200 MSPS.
Availability
THS4130CDGKR is available at Aetrix Electronics and suitable for medical imaging systems, high-resolution data acquisition, test and measurement instruments, and industrial process monitoring requiring stable component supply across extended temperature ranges.
Supply support for THS4130CDGKR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in high-performance amplifiers and signal-chain solutions.
The THS413x product line was engineered specifically for demanding differential signal-path applications - including ultrasound, instrumentation, and communications - where low noise, high linearity, and robust common-mode rejection are non-negotiable.
FAQ
What is the function of the VOCM pin on the THS4130CDGKR?
The VOCM pin on the THS4130CDGKR sets the DC common-mode voltage of the differential output pair. Applying a stable voltage (e.g., mid-rail or ADC reference) to VOCM directly controls the output swing centerpoint, enabling seamless interfacing with differential-input ADCs regardless of supply voltage. A 0.1 µF bypass capacitor is recommended to minimize noise coupling into this critical control node. This feature is integral to the THS4130CDGKR's role in precision level-shifting applications.
Does the THS4130CDGKR support single-supply operation?
Yes, the THS4130CDGKR supports single-supply operation from 5 V to 30 V, with specified performance across the full range. At 5 V, it delivers 165 MHz bandwidth and –101 dBc THD at 250 kHz. Input common-mode range extends from –3.77 V to 4.3 V (referred to VCC–), and output swing reaches 1.2 V to 3.8 V (RL = 1 kΩ), making the THS4130CDGKR viable for low-voltage portable instrumentation without dual-rail generation.
How does the power-down feature work on the THS4130CDGKR?
The THS4130CDGKR's PD pin is active-low: pulling it to VCC– disables the amplifier and reduces quiescent current to 0.86 mA. An internal 250 kΩ pull-up to VCC+ keeps the device enabled if PD is left floating. In shutdown, outputs enter high-impedance state (>1 MΩ), preventing loading of downstream stages. This behavior is explicitly characterized in the THS4130CDGKR datasheet and validated for use in multiplexed analog signal paths.
What package type is used for the THS4130CDGKR?
The THS4130CDGKR uses the DGK package: an 8-pin VSSOP (Very Small Outline Package) measuring 3.0 mm × 3.0 mm with 0.65 mm lead pitch and an exposed thermal pad on the underside. The thermal pad is electrically isolated and must be soldered to a large PCB copper plane for optimal thermal performance - a requirement explicitly documented in the THS4130CDGKR thermal characteristics table.
Can the THS4130CDGKR drive heavy capacitive loads?
The THS4130CDGKR is not optimized for direct capacitive loading >10 pF. To maintain stability, a series resistor (≥20 Ω) must be placed between each output and the load capacitance, as shown in Figure 9-1 of the THS4130CDGKR datasheet. This isolation network prevents peaking and oscillation while preserving bandwidth - a design constraint confirmed across all operating conditions in the THS4130CDGKR's typical characteristics section.
THS4130CDGKR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Amplifier Type:
- Differential
- Number of Circuits:
- 1
- Output Type:
- Differential
- Slew Rate:
- 52V/µs
- Gain Bandwidth Product:
- 225 MHz
- -3db Bandwidth:
- 150 MHz
- Current - Input Bias:
- 2 µA
- Voltage - Input Offset:
- 200 µV
- Current - Supply:
- 14mA
- Current - Output / Channel:
- 85 mA
- Voltage - Supply Span (Min):
- 5 V
- Voltage - Supply Span (Max):
- 30 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-VSSOP
THS4130CDGKR FAQ
1.How can I place an order for THS4130CDGKR through Aetrix?
Please submit a Request for Quotation (RFQ) for THS4130CDGKR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for THS4130CDGKR reliable?
The price and inventory of THS4130CDGKR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for THS4130CDGKR is usually 5 days.
3.What payment methods are accepted for THS4130CDGKR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for THS4130CDGKR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for THS4130CDGKR?
THS4130CDGKR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your THS4130CDGKR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for THS4130CDGKR?
For technical support, including THS4130CDGKR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your THS4130CDGKR requirements.
6.How does Aetrix verify that THS4130CDGKR is sourced from the original manufacturer or authorized distributors?
All THS4130CDGKR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that THS4130CDGKR meets industry standards.
7.What is the process for return or replacement of THS4130CDGKR?
All THS4130CDGKR units undergo pre-shipment inspection (PSI). If there is an issue with THS4130CDGKR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The THS4130CDGKR part is unused and in its original packaging.
Return procedure for THS4130CDGKR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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