Texas Instruments THS4130CDGN
- Part No.:
- THS4130CDGN
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width) Exposed Pad
- Datasheet:
-
THS4130CDGN.pdf
- Description:
- IC OPAMP DIFF 1 CIRCUIT 8HVSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
THS4130CDGN from Texas Instruments is a fully differential input/output amplifier optimized for high-speed, low-noise signal conditioning in precision analog front-ends. It delivers 170 MHz small-signal bandwidth, 51 V/µs slew rate, –102 dBc THD at 250 kHz (±15 V supply), and 1.25 nV/√Hz input voltage noise. Its active power-down pin (PD) reduces quiescent current to 0.86 mA and enables use in battery-sensitive medical ultrasound and ADC driver applications.
For engineers reviewing the THS4130CDGN datasheet, THS4130CDGN pinout, THS4130CDGN application, or THS4130CDGN equivalent, key selection considerations include differential output impedance control via feedback network configuration, VOCM pin–driven common-mode level setting, thermal performance of the HVSSOP-8 PowerPAD™ package, and trade-offs between THS4130 (power-down enabled) and THS4131 (no PD) variants.
Technical Context
The THS4130CDGN implements a true fully differential signal path using TI's high-voltage complementary bipolar process, supporting dual supplies up to ±15 V or single supply from 5 V to 30 V. Its architecture includes matched internal 10-kΩ resistors tied to the VOCM error amplifier, enabling precise common-mode output control independent of gain configuration.
Power-down mode is activated by pulling the PD pin ≤1.4 V above VCC–, placing outputs in high-impedance state (>1 MΩ differential output impedance). The device achieves 95 dB CMRR at 800 kHz and maintains stable operation with capacitive loads ≥10 pF when series output resistors (e.g., 20 Ω) are used per output leg.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Small-signal bandwidth | 170 MHz at ±15 V supply - enables baseband signal amplification up to UHF without gain peaking or phase degradation |
| Slew rate | 51 V/µs - supports fast transient response for pulse-shaped signals in ultrasound transmit/receive chains |
| Total harmonic distortion | –102 dBc at 2 VPP, 250 kHz, ±15 V - ensures minimal even-order distortion critical for high-fidelity ADC driving |
| Input voltage noise | 1.25 nV/√Hz at 10 kHz - preserves SNR in low-amplitude sensor interfaces like piezoelectric transducer preamps |
| Quiescent current (shutdown) | 0.86 mA - allows >90% supply current reduction during idle cycles in portable diagnostic equipment |
| Common-mode rejection ratio | 95 dB at 800 kHz - rejects coupled EMI in noisy industrial or automotive environments without external filtering |
| Supply voltage range | ±2.5 V to ±15 V (dual) or 5 V to 30 V (single) - accommodates legacy ±15 V systems and modern low-voltage embedded designs |
Pinout & Package
HVSSOP-8 (DGN) package with exposed thermal pad on underside; requires connection to large copper plane for optimal thermal dissipation (RθJB = 30.0 °C/W). Thermal pad is electrically isolated and may be connected to any pin or ground.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN+ | Differential input (non-inverting) | Accepts positive half of fully differential or single-ended input signal; high-impedance node (215 MΩ common-mode RIN) |
| PD | Active-low power-down control | Pull ≤1.4 V above VCC– to disable amplifier; internal 250-kΩ pull-up to VCC+ keeps device active if floating |
| VCC– | Negative supply rail | Supports dual-supply operation down to –15 V; absolute max rating is 33 V total across VCC+ and VCC– |
| VOUT– | Differential output (inverted) | Delivers complementary output signal; internal 10-kΩ resistor ties to VOCM error amplifier for common-mode regulation |
| VIN– | Differential input (inverting) | Accepts negative half of differential input or reference node for single-ended configuration |
| VOCM | Output common-mode voltage setpoint | DC voltage applied here defines midpoint of VOUT+ and VOUT– swing; bypass with 0.1-µF capacitor to suppress noise |
| VCC+ | Positive supply rail | Supports dual-supply operation up to +15 V; PSRR = 98 dB (dc) minimizes supply ripple coupling into output |
| VOUT+ | Differential output (non-inverted) | Delivers primary output signal; output resistance = 41 Ω (open-loop); drives 7-Ω loads up to 85 mA (±15 V) |
Key Features
| Feature | Design Value |
|---|---|
| Fully differential I/O architecture | Enables single-ended-to-differential conversion without external baluns, reducing PCB area and component count in data acquisition systems |
| Active power-down with <1.5 mA shutdown current | Extends battery life in portable ultrasound probes and handheld test equipment by disabling signal path while preserving bias states |
| VOCM pin for programmable output common-mode level | Allows direct interface to ADC reference voltages (e.g., 2.5 V or 1.25 V) without level-shifting circuitry or external op amps |
| 95 dB CMRR at 800 kHz | Rejects electromagnetic interference in motor drive feedback loops and industrial sensor interfaces without additional shielding |
| HVSSOP-8 PowerPAD™ thermal package | Reduces junction-to-board thermal resistance to 30.0 °C/W-critical for sustained 170 MHz operation in compact medical enclosures |
Applications
| Medical Ultrasound Transmit/Receive | Differential ADC Driver |
|---|---|
Use Scenario: Amplifying weak echo signals from piezoelectric transducers while rejecting cable-induced common-mode noise. IC Role / Device Role / Timing Role: Fully differential amplifier providing gain, common-mode level shifting, and noise-rejecting signal conditioning before digitization. Use Value: 1.25 nV/√Hz input noise and –102 dBc THD preserve dynamic range and image resolution in 12-bit+ ultrasound systems. |
Use Scenario: Driving high-resolution SAR or pipeline ADCs requiring matched differential inputs and precise common-mode voltage alignment. IC Role / Device Role / Timing Role: Signal conditioner that converts single-ended sensor outputs to balanced differential signals synchronized to ADC sampling clock. Use Value: 170 MHz bandwidth and 51 V/µs slew rate support >1 MSPS sampling rates with minimal settling error and harmonic distortion. |
| Single-Ended to Differential Conversion | Differential Antialiasing Filter Driver |
Use Scenario: Converting legacy single-ended analog outputs (e.g., from DACs or sensors) into differential format for noise-immune transmission over PCB traces or cables. IC Role / Device Role / Timing Role: Gain stage with VOCM-controlled output centering, eliminating need for external common-mode bias networks. Use Value: Internal 10-kΩ output resistors and matched input structure ensure <0.1% amplitude/phase imbalance, minimizing residual common-mode error. |
Use Scenario: Buffering and amplifying output of passive antialiasing filters before feeding differential ADC inputs in data acquisition systems. IC Role / Device Role / Timing Role: High-Z input buffer with low output impedance to prevent filter loading and maintain designed cutoff frequency accuracy. Use Value: 41 Ω open-loop output resistance and 85 mA drive capability maintain filter transfer function integrity under varying ADC input capacitance loads. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fully differential amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| THS4131CDGN | No power-down pin; quiescent current remains ~13 mA at ±15 V (vs. 0.86 mA shutdown for THS4130CDGN) | Better suited for always-on instrumentation where power cycling is unnecessary | Select THS4131CDGN when continuous operation eliminates need for PD control logic and PCB routing overhead |
| LMH5401RTVT | Higher bandwidth (1.8 GHz), no VOCM pin, fixed 1-V common-mode output; requires external level-shifting for non-1-V ADCs | Targeted at RF and high-speed communications, not precision low-noise analog front-ends | Choose LMH5401RTVT only when >1-GHz bandwidth is mandatory and VOCM flexibility is secondary to speed |
Compared with THS4131CDGN and LMH5401RTVT, THS4130CDGN uniquely balances ultra-low noise (1.25 nV/√Hz), programmable VOCM, and sub-mA shutdown-making it the only option among the three suitable for battery-powered, high-SNR medical imaging front-ends requiring flexible common-mode control.
Availability
THS4130CDGN is available at Aetrix Electronics and suitable for medical ultrasound systems, high-resolution data acquisition, and industrial sensor signal conditioning requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for THS4130CDGN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in high-performance amplifier design and manufacturing.
The THS413x family was engineered specifically for demanding differential signal chain applications-including medical imaging, test equipment, and high-fidelity data converters-where low noise, wide bandwidth, and precise common-mode control are essential.
FAQ
What is the function of the VOCM pin on the THS4130CDGN?
The VOCM pin on the THS4130CDGN sets the DC common-mode voltage of the differential outputs (VOUT+ and VOUT–). Applying a stable voltage from a low-impedance source directly establishes the output midpoint-enabling seamless interfacing with ADC reference levels such as 1.25 V or 2.5 V. Leaving VOCM unconnected defaults it to mid-rail (VCC+ + VCC–)/2, but a 0.1-µF bypass capacitor is recommended to suppress noise coupling. This feature eliminates external level-shifting circuitry in THS4130CDGN-based designs.
How does the power-down feature of the THS4130CDGN operate?
The THS4130CDGN enters power-down mode when its PD pin is pulled to a voltage ≤1.4 V above VCC–, reducing quiescent current to 0.86 mA. An internal 250-kΩ pull-up resistor to VCC+ keeps the device active if PD is left floating. In shutdown, outputs go high-impedance (>1 MΩ), isolating downstream circuitry. This behavior is confirmed in the Electrical Characteristics table (ICC(SD)) and Functional Block Diagram section of the THS4130CDGN datasheet, making it ideal for duty-cycled ultrasound beamforming.
Can the THS4130CDGN drive heavy capacitive loads?
The THS4130CDGN is internally compensated for maximum bandwidth and slew rate, making it sensitive to capacitive loading >10 pF. To maintain stability, a 20-Ω series resistor must be placed in each output path (VOUT+ and VOUT–) when driving such loads-as specified in Section 9.1.2 of the THS4130CDGN datasheet. This isolation technique prevents high-frequency ringing and preserves phase margin, especially critical in PCB layouts with long traces to ADC inputs or connectors.
What is the thermal performance advantage of the HVSSOP-8 (DGN) package for the THS4130CDGN?
The THS4130CDGN in HVSSOP-8 (DGN) package features an exposed thermal pad that lowers junction-to-board thermal resistance to 30.0 °C/W-nearly half that of SOIC-8 (69.8 °C/W) and significantly better than VSSOP-8 (83.2 °C/W). When soldered to a large copper plane, this enables sustained 170 MHz operation at full output swing without thermal throttling, which is essential in compact, fanless enclosures used in portable THS4130CDGN-based ultrasound systems.
How does resistor matching affect THS4130CDGN performance in differential applications?
Resistor mismatch in the THS4130CDGN's external feedback network directly degrades output balance, CMRR, PSRR, and second-harmonic distortion. As stated in Section 9.1.1.1, using 1% tolerance or better resistors is required to minimize imbalance-induced common-mode error. Table 9-1 in the THS4130CDGN datasheet specifies exact RG/RF values per gain setting (e.g., 390 Ω each for G = 1 V/V) to ensure optimal performance-deviations increase distortion and reduce effective resolution in THS4130CDGN-driven ADC systems.
THS4130CDGN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Amplifier Type:
- Differential
- Number of Circuits:
- 1
- Output Type:
- Differential
- Slew Rate:
- 52V/µs
- Gain Bandwidth Product:
- 225 MHz
- -3db Bandwidth:
- 150 MHz
- Current - Input Bias:
- 2 µA
- Voltage - Input Offset:
- 200 µV
- Current - Supply:
- 14mA
- Current - Output / Channel:
- 85 mA
- Voltage - Supply Span (Min):
- 5 V
- Voltage - Supply Span (Max):
- 30 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-HVSSOP
THS4130CDGN FAQ
1.How can I place an order for THS4130CDGN through Aetrix?
Please submit a Request for Quotation (RFQ) for THS4130CDGN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for THS4130CDGN reliable?
The price and inventory of THS4130CDGN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for THS4130CDGN is usually 5 days.
3.What payment methods are accepted for THS4130CDGN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for THS4130CDGN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for THS4130CDGN?
THS4130CDGN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your THS4130CDGN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for THS4130CDGN?
For technical support, including THS4130CDGN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your THS4130CDGN requirements.
6.How does Aetrix verify that THS4130CDGN is sourced from the original manufacturer or authorized distributors?
All THS4130CDGN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that THS4130CDGN meets industry standards.
7.What is the process for return or replacement of THS4130CDGN?
All THS4130CDGN units undergo pre-shipment inspection (PSI). If there is an issue with THS4130CDGN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The THS4130CDGN part is unused and in its original packaging.
Return procedure for THS4130CDGN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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