Texas Instruments THS4505D
- Part No.:
- THS4505D
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
THS4505D.pdf
- Description:
- IC OPAMP DIFF 1 CIRCUIT 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:345
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Product details
Overview
THS4505D from Texas Instruments is a high-linearity, fully differential amplifier optimized as an ADC driver for 12-bit, 80-MSps data converters. It delivers 260 MHz small-signal bandwidth, –73 dBc third-order intermodulation distortion at 30 MHz, and 1800 V/µs slew rate under ±5 V supply, enabling high-fidelity signal conditioning in wireless receiver chains and active differential filtering applications.
For engineers reviewing the THS4505D datasheet, THS4505D pinout, THS4505D application, or THS4505D equivalent, this page provides verified specifications, SOIC-8 package details, differential I/O architecture context, VOCM-controlled output common-mode setting, and validated alternatives for single-ended-to-differential conversion and precision line driving.
Technical Context
The THS4505D implements a fully differential voltage-feedback architecture with independent input and output common-mode control paths. Its input stage supports rail-to-rail common-mode range down to the negative supply rail (–5.7 V at ±5 V), while the VOCM pin enables precise setting of the differential output's common-mode voltage between 1.3 V and 3.7 V in single-supply mode or ±2.6 V in dual-supply mode.
It features matched internal transconductance stages and laser-trimmed resistor networks to achieve 70 dB minimum CMRR and –65 dB typical output balance error at 100 kHz. The amplifier lacks power-down functionality-distinguishing it from the pin-compatible THS4504-and is characterized for stable operation with 499 Ω feedback resistors and 800 Ω differential loads.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Small-signal bandwidth | 260 MHz at G = 1 (±5 V): enables baseband and IF signal amplification up to UHF without gain peaking or phase degradation. |
| Slew rate | 1800 V/µs (±5 V): supports full-scale transient response for 2 VPP signals within 0.8 ns rise time, critical for fast-settling ADC interfaces. |
| IMD3 distortion | –73 dBc at 30 MHz (±5 V): ensures <0.2% harmonic corruption in wideband communication receivers operating near Nyquist. |
| OIP3 | 29 dBm at 30 MHz (±5 V, referenced to 50 Ω): confirms robust linearity for high-dynamic-range RF front-end buffering. |
| Input voltage noise | 8 nV/√Hz (>1 MHz): contributes <0.5 LSB noise floor when driving 12-bit ADCs with ≥100 kSPS effective sampling rates. |
| Quiescent current | 16–25 mA (±5 V, –40°C to +85°C): balances performance and thermal load in compact SOIC-8 PCB layouts with no heatsink required. |
| Common-mode input range | –5.7 V to +2.6 V (±5 V): allows direct interfacing with bipolar DAC outputs or ground-referenced sensors without level-shifting circuitry. |
Pinout & Package
THS4505D is housed in an 8-pin SOIC (D) package with exposed pad not electrically connected. Thermal resistance θJA = 97.5°C/W enables operation up to +85°C ambient with standard PCB copper pour.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN− | Inverting input | Differential input node; accepts single-ended or complementary signals; supports common-mode range down to VS−. |
| VIN+ | Non-inverting input | Differential input node; matched to VIN− for >70 dB CMRR; requires symmetrical layout for optimal balance. |
| VOCM | Output common-mode control | Analog input setting DC offset of VOUT+ and VOUT−; 25 kΩ || 1 pF impedance; floats to ~0 V if unconnected (dual-supply). |
| VS+ | Positive supply | Accepts +5 V, +12 V, or +15 V in single-supply mode; must be decoupled with 0.1 µF ceramic + 10 µF bulk capacitor. |
| VOUT+ | Positive differential output | Delivers amplified, phase-inverted signal relative to VOUT−; drives 800 Ω differential loads or 50 Ω single-ended via transformer. |
| VS− | Negative supply | Accepts –5 V, –12 V, or –15 V in dual-supply mode; connects to ground in single-supply configurations (VS− = GND). |
| VOUT− | Negative differential output | Delivers amplified, non-inverted signal relative to VOUT+; maintains tight amplitude/phase matching with VOUT+ (–65 dB balance error). |
| PD | Power-down disable | No internal connection on THS4505D; left unconnected or tied to VS+ to ensure always-on operation (unlike THS4504). |
Key Features
| Feature | Design Value |
|---|---|
| Fully differential architecture | Eliminates even-order harmonics and common-mode noise pickup; reduces EMI susceptibility in mixed-signal PCBs. |
| Output common-mode control (VOCM) | Enables precise alignment of differential output to ADC reference mid-point (e.g., 2.5 V), minimizing code-dependent offset errors. |
| Input common-mode range includes VS− | Supports ground-referenced sensor inputs or DAC outputs without external level shifters, reducing BOM count and layout area. |
| Wide supply range (±5 V to ±7.5 V / 4.5 V to 15 V) | Allows reuse across multiple system rails-from low-voltage portable receivers to high-voltage instrumentation front ends. |
| 260 MHz bandwidth with –73 dBc IMD3 | Meets SFDR requirements for LTE/WiMAX IF sampling at 30–40 MHz while maintaining <12-bit ENOB up to 40 MHz. |
Applications
| Wireless Baseband Receiver | High-Speed Data Acquisition |
|---|---|
|
Use Scenario: Conditioning I/Q signals from quadrature demodulators prior to 12-bit, 80-MSps ADC sampling in LTE femtocell receivers. IC Role / Device Role / Timing Role: Fully differential ADC driver with VOCM-adjusted output swing matching ADC reference voltage. Use Value: –73 dBc IMD3 at 30 MHz preserves adjacent-channel rejection; 260 MHz bandwidth accommodates 20-MHz LTE channel bandwidth with margin. |
Use Scenario: Driving dual-channel simultaneous-sampling ADCs in oscilloscope front ends requiring matched gain and phase. IC Role / Device Role / Timing Role: Precision differential line driver with <0.8 ns rise time and –65 dB output balance error. Use Value: 1800 V/µs slew rate ensures <100 ns settling to 0.01% for 4 VPP steps; matched outputs minimize skew-induced timing jitter. |
| Active Differential Filter Stage | Single-Ended to Differential Conversion |
|
Use Scenario: Implementing 4th-order Chebyshev anti-aliasing filters with tunable cutoff using THS4505D-based biquad sections. IC Role / Device Role / Timing Role: High-speed op-amp core in fully differential filter topology with programmable VOCM setpoint. Use Value: 70 dB CMRR suppresses power-supply ripple coupling into filter passband; 8 nV/√Hz noise avoids degrading SNR below 70 dB. |
Use Scenario: Converting single-ended analog outputs from precision DACs or sensors into balanced differential signals for noise-immune transmission. IC Role / Device Role / Timing Role: Unity-gain differential amplifier with rail-to-rail input and VOCM-configurable output common-mode. Use Value: Input common-mode range extending to VS− allows direct interface with 0–5 V DACs; VOCM pin sets output midpoint to match downstream receiver. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fully differential amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| THS4504D | Identical SOIC-8 pinout and AC/DC specs, but includes PD pin for 800 µA power-down mode; quiescent current rises to 25 mA max in active state. | Required where system-level power cycling or standby modes are implemented; unsuitable if PD pin routing adds layout complexity. | Select THS4504D only if dynamic power management is needed; THS4505D offers simpler biasing and guaranteed always-on behavior. |
| THS4131CD | 15 V supply, 150 MHz bandwidth, 51 V/µs slew rate, 1.3 nV/√Hz noise; MSOP-8 package; no VOCM pin-output common-mode fixed at VS/2. | Better suited for lower-frequency, low-noise applications (e.g., audio, precision instrumentation); lacks VOCM flexibility for ADC interface tuning. | Choose THS4131CD for sub-50 MHz designs prioritizing ultra-low noise over bandwidth; THS4505D remains optimal for >100 MHz ADC drivers. |
Compared with THS4504D and THS4131CD, THS4505D uniquely combines 260 MHz bandwidth, –73 dBc IMD3 at 30 MHz, and VOCM-adjustable output common-mode in a standard SOIC-8 footprint-making it the preferred choice for high-SFDR, software-defined radio and high-speed data acquisition systems.
Availability
THS4505D is available at Aetrix Electronics and suitable for wireless infrastructure, test equipment, and medical imaging systems requiring stable component supply, long-term production continuity, and TI-qualified performance across –40°C to +85°C.
Supply support for THS4505D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-performance amplifier design.
The THS4505D belongs to TI's THS45xx family of fully differential amplifiers, engineered specifically for high-fidelity ADC driving, RF receiver chain signal conditioning, and precision differential signal generation in communications and instrumentation.
FAQ
What is the maximum recommended supply voltage for THS4505D?
The absolute maximum supply voltage for THS4505D is ±8.25 V (16.5 V total), but the recommended operating range is ±5 V to ±7.5 V for dual supply or 4.5 V to 15 V for single supply. Operating beyond ±7.5 V risks exceeding the 1.02 W package power rating at +25°C ambient and may degrade distortion performance above 200 mW junction dissipation.
Does THS4505D support single-supply operation?
Yes, THS4505D supports true single-supply operation from 4.5 V to 15 V. With VS− grounded, the input common-mode range extends from –0.7 V to +2.6 V and VOCM can be biased between 1.3 V and 3.7 V to set the output common-mode level-enabling direct interface with 2.5 V or 3.3 V ADC references without level-shifting circuitry.
What is the function of the PD pin on THS4505D?
The PD (power-down) pin on THS4505D is not internally connected-it is a no-connect terminal. Unlike the THS4504D, the THS4505D has no power-down capability and operates continuously when powered. Leaving PD unconnected or tying it to VS+ ensures reliable always-on functionality without risk of unintended shutdown.
How does VOCM affect THS4505D output swing in single-supply mode?
In single-supply mode (e.g., VS+ = 5 V, VS− = GND), the VOCM pin directly sets the average DC voltage of VOUT+ and VOUT−. When VOCM = 2.5 V, the differential output swings symmetrically around 2.5 V (e.g., 2.5 V ± 3.3 V). This allows precise alignment to the mid-scale reference of 5 V full-scale ADCs, minimizing offset-induced integral nonlinearity.
Can THS4505D drive 50 Ω differential loads?
THS4505D is characterized for 800 Ω differential loads but can drive 50 Ω differential loads with external series termination. At ±5 V supply, it delivers ±7.4 V differential swing into 1 kΩ and sustains 100 mA output current into 20 Ω-confirming capability to drive 50 Ω with appropriate gain-setting resistors and attention to thermal derating above 85°C ambient.
THS4505D Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- Differential
- Number of Circuits:
- 1
- Output Type:
- Differential
- Slew Rate:
- 1800V/µs
- Gain Bandwidth Product:
- 210 MHz
- -3db Bandwidth:
- 260 MHz
- Current - Input Bias:
- 4 µA
- Voltage - Input Offset:
- 4 mV
- Current - Supply:
- 16mA
- Current - Output / Channel:
- 130 mA
- Voltage - Supply Span (Min):
- 4.5 V
- Voltage - Supply Span (Max):
- 15 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
THS4505D FAQ
1.How can I place an order for THS4505D through Aetrix?
Please submit a Request for Quotation (RFQ) for THS4505D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for THS4505D reliable?
The price and inventory of THS4505D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for THS4505D is usually 5 days.
3.What payment methods are accepted for THS4505D?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for THS4505D transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for THS4505D?
THS4505D orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your THS4505D order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for THS4505D?
For technical support, including THS4505D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your THS4505D requirements.
6.How does Aetrix verify that THS4505D is sourced from the original manufacturer or authorized distributors?
All THS4505D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that THS4505D meets industry standards.
7.What is the process for return or replacement of THS4505D?
All THS4505D units undergo pre-shipment inspection (PSI). If there is an issue with THS4505D, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The THS4505D part is unused and in its original packaging.
Return procedure for THS4505D:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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