Texas Instruments THS7365IPWR
- Part No.:
- THS7365IPWR
- Manufacturer:
- Texas Instruments
- Category:
- Video Amps and Modules
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
THS7365IPWR.pdf
- Description:
- IC AMP BUFFER 20TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,833
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Product details
Overview
THS7365IPWR from Texas Instruments is a 6-channel video amplifier IC with three standard-definition (SD) and three high-definition (HD) channels, each featuring bypassable sixth-order Butterworth low-pass filters (–3 dB at 9.5 MHz for SD, 36 MHz for HD), 6-dB fixed gain, rail-to-rail output swing, and single-supply operation from +2.7 V to +5 V. It serves as a video line driver in set-top box and Blu-ray player output buffering.
For engineers reviewing the THS7365IPWR datasheet, THS7365IPWR pinout, THS7365IPWR application, or THS7365IPWR equivalent, key selection considerations include SD/HD channel separation, filter bypass control logic, 75-Ω driving capability per channel, differential gain/phase performance (0.2%/0.3°), and TSSOP-20 package thermal characteristics.
Technical Context
The THS7365IPWR integrates six independent video amplifiers-three optimized for SD signals (CVBS, S-Video Y'/C', 480i/576i) and three for HD signals (Y'/PB/PR, 720p/1080i/1080p30)-each with dedicated sixth-order LPF and individual enable/bypass controls. Its SiGe BiCom3X process enables low quiescent current (20.7 mA at 3.3 V) while maintaining rail-to-rail output swing within 100 mV of rails.
Input coupling supports DC-coupled mode with 300-mV output level shift, AC-coupled sync-tip clamp for CVBS/Y'/R'G'B', or external-bias AC coupling for C'/PB/PR. Logic inputs (Disable SD/HD, Bypass SD/HD) are TTL-compatible and must not float; enable/disable timing is under 140 ns.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage | +2.7 V to +5 V single supply: Enables direct integration into 3.3-V or 5-V video subsystems without level-shifting. |
| SD filter –3 dB bandwidth | 9.5 MHz: Matches NTSC/PAL DAC reconstruction and anti-aliasing requirements for 480i/576i signals. |
| HD filter –3 dB bandwidth | 36 MHz: Supports full bandwidth of 720p/1080i signals with <0.1% differential gain error. |
| Gain | 6 dB (2×): Fixed non-inverting gain simplifies PCB layout and eliminates external feedback component variation. |
| Rail-to-rail output swing | Swings within 100 mV of rails: Allows direct driving of 75-Ω loads with AC or DC coupling and full sync-tip dynamic range. |
| Total quiescent current | 20.7 mA at 3.3 V: Enables low-power video buffering in portable or thermally constrained consumer devices. |
| Differential gain/phase | 0.2%/0.3° (NTSC): Meets broadcast-grade color fidelity requirements without post-amplifier correction. |
Pinout & Package
TSSOP-20 package (RoHS-compliant, green, lead-free); 6.5 mm × 4.4 mm footprint with 0.65 mm pitch; thermal pad not present; JEDEC MS-013 variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 (SD1–3 IN) | SD video input | Accepts CVBS, Y', or R'G'B' baseband signals; supports DC-coupled (300-mV shift) or AC-coupled (sync-tip clamp) biasing. |
| 7, 8, 9 (HD1–3 IN) | HD video input | Accepts Y'/PB/PR or G'B'R' signals; AC-coupling requires external resistor to VS+ for bias. |
| 20, 19, 18 (SD1–3 OUT) | SD video output | Drives 75-Ω loads directly; rail-to-rail swing supports both AC- and DC-coupled termination. |
| 12, 13, 14 (HD1–3 OUT) | HD video output | Delivers full HD bandwidth with <0.1% differential gain; output impedance ≤1.7 Ω at 30 MHz in filter mode. |
| 10 (Bypass SD) | SD filter control | Logic high disables all three SD channel filters; must be tied to VS+ or GND-no floating allowed. |
| 11 (Bypass HD) | HD filter control | Logic high disables all three HD channel filters; 5-ns switching time enables real-time format adaptation. |
| 17 (Disable SD) | SD channel shutdown | Logic high disables SD outputs (IQ drops to 6.9 mA max); used for power gating during HD-only operation. |
| 15 (Disable HD) | HD channel shutdown | Logic high disables HD outputs (IQ drops to 13.8 mA max); supports dynamic power scaling in multi-format systems. |
| 5 (VS+) | Positive supply | Accepts 2.7–5 V; decoupling capacitor required at pin for stability across SD/HD bandwidths. |
| 16 (GND) | Ground reference | Common return for all analog and digital circuitry; requires low-impedance PCB plane connection. |
Key Features
| Feature | Design Value |
|---|---|
| Six independent video channels | Three SD + three HD paths allow simultaneous processing of legacy and modern video formats without multiplexing delay. |
| Bypassable sixth-order Butterworth filters | Enables system-level flexibility: use filters for DAC reconstruction or bypass for ADC sampling paths. |
| Rail-to-rail output stage | Supports both AC-coupled (capacitor-coupled) and DC-coupled (direct-connected) 75-Ω video loads without external level-shifting. |
| Sync-tip clamp for AC-coupled inputs | Preserves black-level accuracy on CVBS/Y'/R'G'B' inputs without external clamping diodes or timing circuits. |
| Low-power disable modes | 0.1 µA shutdown current when both SD and HD are disabled-critical for battery-backed video standby states. |
Applications
| Set-Top Box Output Buffering | PVR/DVR Output Buffering |
|---|---|
Use Scenario: Driving composite (CVBS), S-Video (Y'/C'), and component (Y'/PB/PR) outputs from a single SoC in a cable/satellite STB. IC Role / Device Role / Timing Role: Video line driver with integrated reconstruction filtering and format-flexible biasing. Use Value: Eliminates six discrete op-amps and external RC filters; reduces BOM count by ≥12 components while meeting SMPTE 253M differential phase spec. | Use Scenario: Buffering decoded video streams to HDMI transmitter and analog outputs in a dual-output PVR. IC Role / Device Role / Timing Role: Simultaneous SD and HD analog output driver with independent channel enable/disable. Use Value: Enables zero-latency switching between SD and HD playback modes via Disable SD/HD pins-no software reconfiguration needed. |
| Blu-ray Player Analog Output | Low-Power Video Monitoring System |
Use Scenario: Providing legacy analog outputs (component Y'/PB/PR) alongside HDMI in a Blu-ray Disc™ player. IC Role / Device Role / Timing Role: HD video buffer with 36-MHz filter bandwidth and <0.1% differential gain for studio-grade color reproduction. Use Value: Meets Macrovision-compliant output specs while delivering 720p/1080i signal integrity without external equalization. | Use Scenario: Driving multiple 75-Ω video feeds (e.g., security camera monitors) from a low-power embedded media processor. IC Role / Device Role / Timing Role: Power-gated video amplifier with 20.7-mA active current and 0.1-µA deep-sleep mode. Use Value: Extends system runtime in battery-powered monitoring units by >40% versus discrete solutions with comparable SNR (78 dB). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar video amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| THS7356IPW | 3-channel SD-only amplifier; no HD channels or HD filters; same TSSOP-20 package and 6-dB gain. | Limited to CVBS/S-Video outputs only; cannot support Y'/PB/PR or 720p/1080i signals. | Select when system requires SD output only and board space/power budget precludes unused HD channels. |
| LMH0387SQ/NOPB | 3G-SDI reclocker with integrated cable driver; no analog video filtering; operates at 2.97 Gbps serial rate. | Designed for digital serial video transport-not baseband analog buffering-requiring serializer/deserializer pairing. | Select for digital video backhaul over coax; not a functional substitute for analog baseband amplification and filtering. |
Compared with THS7365IPWR, THS7356IPW offers identical SD performance in smaller footprint but lacks HD capability, while LMH0387SQ/NOPB addresses digital video infrastructure rather than analog line driving-neither is pin-compatible nor functionally interchangeable.
Availability
THS7365IPWR is available at Aetrix Electronics and suitable for set-top box output buffering, PVR/DVR analog output stages, and Blu-ray player legacy video interfaces requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for THS7365IPWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with broad industrial, automotive, and consumer design expertise.
The THS7365IPWR belongs to TI's high-fidelity video amplifier product line, engineered specifically for multi-format consumer video equipment requiring simultaneous SD and HD analog output buffering with minimal external components.
FAQ
What is the maximum operating temperature for the THS7365IPWR?
The THS7365IPWR is rated for continuous operation from –40°C to +85°C ambient temperature. Its maximum junction temperature for long-term reliability is +125°C, and absolute maximum junction temperature under any condition is +150°C. Thermal design must ensure θJA ≤ 88°C/W (JEDEC High-K board) to maintain safe silicon temperatures at full load.
Can the THS7365IPWR drive two 75-Ω loads simultaneously per channel?
Yes, the THS7365IPWR is explicitly designed to drive two 75-Ω video lines per channel. Its rail-to-rail output stage delivers ±90 mA output current and maintains specified differential gain/phase (0.2%/0.3°) and group delay variation (<10 ns) under this dual-load condition, as confirmed in TI's SBOS467 datasheet Figure 1 and Electrical Characteristics tables.
How does the sync-tip clamp function on THS7365IPWR SD inputs?
The THS7365IPWR implements an internal transparent sync-tip clamp on SD inputs (pins 1–3) for AC-coupled CVBS, Y', or R'G'B' signals. When enabled, it restores DC level using the sync tip without external components, preserving black-level accuracy. Clamp charge current is 140–200 µA at –0.1 V input, and the feature is inactive in DC-coupled or bypass modes.
What is the purpose of the NC pins on the THS7365IPWR TSSOP-20 package?
Pins 4 and 6 of the THS7365IPWR are designated NC (no internal connection). TI's datasheet recommends connecting them to GND for mechanical stability and noise immunity-though they carry no electrical function. Leaving them floating is not advised, as it may increase susceptibility to EMI or cause unintended coupling in high-density layouts.
Does the THS7365IPWR support DC-coupled input with AC-coupled output?
Yes, the THS7365IPWR supports mixed coupling configurations. Its 300-mV output level shift enables DC-coupled inputs while driving AC-coupled 75-Ω loads via series capacitors. This configuration preserves full sync-tip dynamic range at the output even with 0-V input, eliminating need for external level-shifters or bias networks in hybrid signal paths.
THS7365IPWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Buffer
- Output Type:
- Rail-to-Rail
- Number of Circuits:
- 6
- -3db Bandwidth:
- 36 MHz
- Slew Rate:
- 500V/µs
- Current - Supply:
- 21.6 mA
- Current - Output / Channel:
- 90 mA
- Voltage - Supply, Single/Dual (±):
- 2.6V ~ 5.5V
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-TSSOP
THS7365IPWR FAQ
1.How can I place an order for THS7365IPWR through Aetrix?
Please submit a Request for Quotation (RFQ) for THS7365IPWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for THS7365IPWR reliable?
The price and inventory of THS7365IPWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for THS7365IPWR is usually 5 days.
3.What payment methods are accepted for THS7365IPWR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for THS7365IPWR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for THS7365IPWR?
THS7365IPWR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your THS7365IPWR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for THS7365IPWR?
For technical support, including THS7365IPWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your THS7365IPWR requirements.
6.How does Aetrix verify that THS7365IPWR is sourced from the original manufacturer or authorized distributors?
All THS7365IPWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that THS7365IPWR meets industry standards.
7.What is the process for return or replacement of THS7365IPWR?
All THS7365IPWR units undergo pre-shipment inspection (PSI). If there is an issue with THS7365IPWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The THS7365IPWR part is unused and in its original packaging.
Return procedure for THS7365IPWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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