Texas Instruments THS7368IPWR
- Part No.:
- THS7368IPWR
- Manufacturer:
- Texas Instruments
- Category:
- Video Amps and Modules
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
THS7368IPWR.pdf
- Description:
- IC AMP FILTER 20TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,071
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
THS7368IPWR from Texas Instruments is a 6-channel single-supply video amplifier with three fixed 9.5-MHz SDTV filters and three selectable SD/ED/HD/Full-HD (9.5/18/36/72 MHz) low-pass filters, 6-dB gain, rail-to-rail output, and 23.4 mA quiescent current at 3.3 V - used in set-top box, PVR, and Blu-ray video output buffering.
For engineers reviewing the THS7368IPWR datasheet, THS7368IPWR pinout, THS7368IPWR application, or THS7368IPWR equivalent, this page delivers verified electrical specs, filter mode truth tables, input coupling options (DC-coupled with 300-mV shift or AC-coupled with sync-tip clamp), and real-world video line driving performance for CVBS, S-Video Y'/C', and component RGB/P'B'P'R' signals.
Technical Context
The THS7368IPWR integrates six independent video buffer channels: SD1–SD3 (CVBS/S-Video Y'/C') with fixed 9.5-MHz sixth-order Butterworth LPFs, and SF1–SF3 (Y'/P'B'/P'R' or RGB) with programmable filter selection via FILTER 1/FILTER 2/BYPASS SF logic inputs. Each channel provides 6-dB gain and rail-to-rail output swing within 100 mV of supply rails.
It supports dual input biasing modes: DC-coupled operation with internal 300-mV output level shift enabling full sync dynamic range from 0-V input, and AC-coupled operation with transparent sync-tip clamp for CVBS/Y'/G'B'R' or external resistor bias for C'/P'B'/P'R'. Disable SD/SF pins allow per-group channel shutdown to 0.1 μA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage | +2.7 V to +5 V single supply - enables direct integration into 3.3-V or 5-V video subsystems without level-shifting. |
| Gain | 6 dB (2×) fixed - provides standard video line driver amplification compatible with 75-Ω termination and DAC output levels. |
| SD filter bandwidth | 9.5 MHz (–1 dB) - matches NTSC/PAL CVBS and S-Video luminance bandwidth requirements. |
| SF filter options | 9.5 / 18 / 36 / 72 MHz or bypass - supports SD, ED, HD, and Full-HD (1080p) component/RGB signal reconstruction. |
| Differential gain/phase | 0.2% / 0.35° (NTSC) - ensures minimal color fidelity degradation in broadcast-quality analog video paths. |
| Quiescent current | 23.4 mA at 3.3 V (all channels active); 0.1 μA in disabled state - meets Energy Star® power-sensitive system requirements. |
| Output drive | Rail-to-rail swing within 100 mV of rails; drives two 75-Ω lines per channel - enables flexible AC/DC coupling and dual-load routing. |
Pinout & Package
TSSOP-20 package (RoHS-compliant, green, lead-free); 6.5 mm × 4.4 mm footprint with 0.65 mm pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SD1 IN – SD3 IN (Pins 1–3) | SD video input | Accepts CVBS, S-Video Y', or S-Video C' signals; each routed through dedicated 9.5-MHz LPF. |
| SF1 IN – SF3 IN (Pins 7–9) | Component/RGB input | Accepts Y'/P'B'/P'R' or G'B'R' signals; filtered by user-selectable LPF (9.5/18/36/72 MHz or bypass). |
| SD1 OUT – SD3 OUT (Pins 20–18) | SD video output | 6-dB amplified, rail-to-rail buffered outputs for CVBS/S-Video; support 75-Ω load driving. |
| SF1 OUT – SF3 OUT (Pins 14–12) | Component/RGB output | 6-dB amplified, rail-to-rail buffered outputs for Y'/P'B'/P'R'; configurable for HD/Full-HD bandwidth. |
| Bypass SD / Bypass SF (Pins 10/11) | Filter control | Logic high disables internal LPF on respective channel group - enables wideband bypass mode up to 300 MHz. |
| Disable SD / Disable SF (Pins 17/15) | Channel enable/disable | Logic high shuts down associated channel group; reduces supply current to 0.1 μA for power gating. |
| Filter 1 / Filter 2 (Pins 6/4) | LPF selection | Binary-encoded inputs selecting SF channel filter: 00=9.5 MHz, 01=18 MHz, 10=36 MHz, 11=72 MHz. |
| VS+ (Pin 5), GND (Pin 16) | Power supply | Single 2.7–5 V supply; no negative rail required - simplifies power architecture in consumer video systems. |
Key Features
| Feature | Design Value |
|---|---|
| Three fixed SD filters + three selectable SF filters | Enables simultaneous CVBS/S-Video and component/RGB output buffering with precise bandwidth matching per signal type. |
| Bypassable sixth-order Butterworth LPFs | Ensures monotonic roll-off and minimal phase distortion for DAC reconstruction or ADC anti-aliasing in video signal chains. |
| DC-coupled mode with 300-mV output shift | Permits full-swing sync tip-to-tip video output from 0-V input - eliminates need for external DC restoration circuitry. |
| AC-coupled sync-tip clamp | Automatically restores DC level on CVBS/Y'/G'B'R' inputs - preserves black level accuracy without external components. |
| Rail-to-rail output stage | Swings within 100 mV of VS+ and GND - supports both AC-coupled (capacitor) and DC-coupled (resistor-terminated) 75-Ω loads. |
Applications
| Set-Top Box Video Output | PVR/DVR Analog Output |
|---|---|
Use Scenario: Driving composite CVBS and S-Video Y'/C' outputs from MPEG decoder ASIC to rear-panel RCA jacks. IC Role / Device Role / Timing Role: 6-channel video buffer with fixed 9.5-MHz SD filters and 6-dB gain, providing impedance matching and signal integrity for 75-Ω coaxial cables. Use Value: Maintains <0.2% differential gain error across NTSC/PAL spectrum, preserving color fidelity without external passive filtering. |
Use Scenario: Buffering decoded video streams to dual-output ports (CVBS + component) in digital video recorder mainboard. IC Role / Device Role / Timing Role: Simultaneous SD (CVBS) and HD-capable (Y'/P'B'/P'R') output driver with independent filter enable/disable per group. Use Value: Programmable SF filter bandwidth (up to 72 MHz) supports 720p/1080i playback while SD channels handle legacy recording playback. |
| Blu-ray Player Component Output | RGB PC Video Interface |
Use Scenario: Driving Y'/P'B'/P'R' component video signals from HDMI-to-analog converter to front-panel component jacks. IC Role / Device Role / Timing Role: SF channel group configured for 36-MHz HD filter to reconstruct 720p/1080i luma/chroma without aliasing. Use Value: 0.35° differential phase error ensures accurate hue reproduction; rail-to-rail output drives dual 75-Ω loads directly. |
Use Scenario: Converting VGA RGB signals (sync-on-green or separate sync) to buffered analog outputs for legacy display interfaces. IC Role / Device Role / Timing Role: SF channels used as RGB line drivers with bypass mode enabled for flat 100-MHz bandwidth and 450-V/µs slew rate. Use Value: >260-MHz small-signal bandwidth and <4 ns group delay variation preserve pixel timing integrity in 1080p@60Hz applications. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar video buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| THS7353IPW | 3-channel SD-only amplifier (no SF/HD filters); 9.5-MHz LPF only; lower quiescent current (12.5 mA @ 3.3 V). | Limited to CVBS/S-Video; cannot support component RGB or HD formats. | Select when only SD outputs are needed and board space/power budget is constrained. |
| LMH0394SQ/NOPB | 3G-SDI reclocking serializer with integrated cable driver; not an analog video amplifier. | Designed for serial digital video (SDI), not analog CVBS/component; requires different signal chain architecture. | Choose only for digital video transport over coax; incompatible with analog video buffering use cases. |
Compared with THS7368IPWR, THS7353IPW offers reduced channel count and no HD capability but lower power, while LMH0394SQ/NOPB serves a fundamentally different domain (digital serial transport vs analog baseband amplification), making it non-substitutable without system-level redesign.
Availability
THS7368IPWR is available at Aetrix Electronics and suitable for set-top box output buffering, PVR/DVR analog output, and Blu-ray player component video applications requiring stable component supply, long-term manufacturability, and RoHS-compliant packaging.
Supply support for THS7368IPWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-fidelity video signal conditioning.
The THS7368IPWR belongs to TI's precision video amplifier product line, engineered specifically for consumer and professional video equipment requiring multi-format analog output buffering with selectable bandwidth and ultra-low distortion.
FAQ
What video standards does the THS7368IPWR support?
The THS7368IPWR supports NTSC/PAL CVBS, S-Video (Y'/C'), and component video (Y'/P'B'/P'R' or RGB) across SD, ED, HD, and Full-HD resolutions. Its SD channels feature fixed 9.5-MHz filters for broadcast analog standards, while SF channels offer programmable 9.5/18/36/72-MHz filters or bypass mode - enabling compliance with 480i, 576i, 720p, 1080i, and 1080p signal bandwidths. THS7368IPWR maintains 0.2%/0.35° differential gain/phase for NTSC, ensuring broadcast-grade color fidelity.
How do I configure the THS7368IPWR for HD component video output?
To configure THS7368IPWR for HD component video (e.g., 720p Y'/P'B'/P'R'), connect SF1–SF3 inputs to the source, set FILTER 1 = HIGH, FILTER 2 = LOW, and BYPASS SF = LOW to select the 36-MHz HD filter. Ensure VS+ = 3.3 V or 5 V, disable SD channels if unused (DISABLE SD = HIGH), and terminate each SF output with 75 Ω to GND or +VS/2. THS7368IPWR delivers 6-dB gain, rail-to-rail swing, and <7.5 ns group delay variation at 27 MHz - preserving timing integrity for HD formats.
Can the THS7368IPWR drive two 75-Ω loads simultaneously per channel?
Yes, the THS7368IPWR rail-to-rail output stage is explicitly rated to drive two 75-Ω loads per channel - confirmed by TI's "Supports Driving Two Video Lines/Channel" feature and output swing specifications (e.g., 3.1 V high swing into 75 Ω at 3.3 V). This capability eliminates need for external splitters or buffers in dual-output designs (e.g., front-panel + rear-panel video jacks). THS7368IPWR maintains <0.2% differential gain error and >46 dB return loss at 6.75 MHz under this load condition.
What are the input coupling options for THS7368IPWR SD channels?
The THS7368IPWR SD channels support two verified input coupling modes: (1) DC-coupled with internal 300-mV output level shift - enabling full sync-tip-to-tip video swing from 0-V input, and (2) AC-coupled with transparent sync-tip clamp - automatically restoring DC level on CVBS, Y', or G'B'R' signals without external diodes or capacitors. THS7368IPWR's datasheet specifies clamp charge current (140–200 μA) and input voltage range (–0.1 V to +1.46 V at 3.3 V) for robust sync detection.
Does THS7368IPWR support power-down mode, and how much current does it draw?
Yes, THS7368IPWR supports hardware-controlled power-down via DISABLE SD and DISABLE SF pins. When both are driven HIGH, total supply current drops to 0.1 μA (typical) - verified across temperature and supply voltage (3.3 V and 5 V). This ultra-low disabled current enables dynamic power gating in energy-sensitive applications like portable media players or standby-mode set-top boxes. THS7368IPWR also features 100-ns enable/disable timing for rapid wake-up.
THS7368IPWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Filter
- Output Type:
- Rail-to-Rail
- Number of Circuits:
- 6
- -3db Bandwidth:
- 9.5 MHz
- Slew Rate:
- 125V/µs
- Current - Supply:
- 24.5 mA
- Current - Output / Channel:
- 90 mA
- Voltage - Supply, Single/Dual (±):
- 2.6V ~ 5.5V
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-TSSOP
THS7368IPWR FAQ
1.How can I place an order for THS7368IPWR through Aetrix?
Please submit a Request for Quotation (RFQ) for THS7368IPWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for THS7368IPWR reliable?
The price and inventory of THS7368IPWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for THS7368IPWR is usually 5 days.
3.What payment methods are accepted for THS7368IPWR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for THS7368IPWR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for THS7368IPWR?
THS7368IPWR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your THS7368IPWR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for THS7368IPWR?
For technical support, including THS7368IPWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your THS7368IPWR requirements.
6.How does Aetrix verify that THS7368IPWR is sourced from the original manufacturer or authorized distributors?
All THS7368IPWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that THS7368IPWR meets industry standards.
7.What is the process for return or replacement of THS7368IPWR?
All THS7368IPWR units undergo pre-shipment inspection (PSI). If there is an issue with THS7368IPWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The THS7368IPWR part is unused and in its original packaging.
Return procedure for THS7368IPWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
THS7368IPWR Tags

-
LT6552CS8#PBF
Analog Devices Inc.

-
LT6205IS5#TRPBF
Analog Devices Inc.

-
LT6206IMS8#TRPBF
Analog Devices Inc.

-
LT6552CDD#PBF
Analog Devices Inc.

-
LT6552IS8#PBF
Analog Devices Inc.

-
LT1252CS8#PBF
Analog Devices Inc.

-
AD818ARZ-REEL7
Analog Devices Inc.

-
MAX4310EUA+
Analog Devices Inc./Maxim Integrated

-
AD829ARZ
Analog Devices Inc.

-
AD810ARZ
Analog Devices Inc.
-
MAX4310ESA+
Analog Devices Inc./Maxim Integrated
-
MAX4313ESA+
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

