My Inquiry
My Account
NXP Semiconductors TJA1041AT/CM,118
- Part No.:
- TJA1041AT/CM,118
- Manufacturer:
- NXP Semiconductors
- Category:
- Drivers, Receivers, Transceivers
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
TJA1041AT/CM,118.pdf
- Description:
- IC TRANSCEIVER HALF 1/1 14SO
- Quantity:
- Payment:
- Shipping:
Inventory:5,073
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TJA1041AT/CM,118 from NXP Semiconductors is a high-speed CAN transceiver designed for automotive in-vehicle networks. It provides bidirectional differential transmit/receive capability compliant with ISO 11898, supports up to 1 Mbit/s data rate, operates from 4.75 V to 5.25 V VCC, features recessive bus DC voltage stabilization via SPLIT pin, and enables local/remote wake-up with source recognition - used in body control modules, powertrain gateways, and ADAS domain controllers.
For engineers reviewing the TJA1041AT/CM,118 datasheet, TJA1041AT/CM,118 pinout, TJA1041AT/CM,118 application, or TJA1041AT/CM,118 equivalent, this page delivers verified operating modes (Normal, Pwon/Listen-only, Standby, Sleep), bus fault diagnostics (bus dominant clamping, TXD-to-RXD short), I/O-level adaptation for 2.8–5.25 V controllers, and ESD robustness (±6 kV HBM on CANH/CANL/SPLIT).
Technical Context
The TJA1041AT/CM,118 implements a fail-safe physical layer per ISO 11898 with five programmable operating modes controlled by STB and EN pins, including Normal mode (full TX/RX), Pwon/Listen-only (RX only, transmitter disabled), and Sleep mode (INH floating, <30 µA VBAT current). Its receiver offers wide common-mode range (−27 V to +40 V) and 70 mV hysteresis for high EMI immunity.
Internal diagnostics include seven flags (UVNOM, UVBAT, pwon, wake-up, wake-up source, bus failure, local failure) accessible via ERR pin, with dedicated detection for TXD dominant clamping (600 µs timeout), RXD recessive clamping, overtemperature (>150 °C shutdown), and bus line shorts to VBAT/GND/VCC - all enabling autonomous node-level fault containment without controller intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Compliance | Fully compliant with ISO 11898-2:2003 for high-speed CAN physical layer implementation. |
| Data Rate | Up to 1 Mbit/s - supports full-speed CAN FD preambles and legacy CAN 2.0B networks. |
| VCC Supply Range | 4.75 V to 5.25 V - ensures stable operation across automotive battery variations (cold crank to load dump). |
| VI/O Range | 2.8 V to 5.25 V - enables direct interface with 3.3 V or 5 V microcontrollers without level shifters. |
| Bus Voltage Tolerance | CANH/CANL/SPLIT withstand −27 V to +40 V - protects against load dump, jump-start, and ground shift events. |
| ESD Robustness | ±6 kV HBM on CANH/CANL/SPLIT - exceeds ISO 10605 requirements for automotive module qualification. |
| Standby Current | 10–30 µA at 12 V VBAT - enables always-on network monitoring with minimal quiescent power draw. |
Pinout & Package
Package: SO14 (plastic small outline, 14 leads, 3.9 mm body width, SOT108-1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TXD (1) | Transmit data input | Digital input from CAN controller; drives differential bus output when active; includes 600 µs dominant timeout protection. |
| GND (2) | Ground reference | Primary signal return path; decoupling capacitor must be placed adjacent to VCC and GND pins. |
| VCC (3) | Transceiver supply | 5 V nominal supply; undervoltage detection triggers Sleep mode if <3.3 V for >10 ms. |
| RXD (4) | Receive data output | CMOS-compatible digital output reflecting bus state; level adapts to VI/O voltage (2.8–5.25 V). |
| VI/O (5) | I/O-level adapter reference | Sets logic thresholds for TXD/STB/EN and output levels for RXD/ERR - eliminates external level-shifting circuitry. |
| EN (6) | Enable control input | Active-HIGH; controls mode transitions with STB to select Normal, Standby, or Go-to-sleep command mode. |
| INH (7) | Inhibit output | Open-drain output controlling external voltage regulators; floats in Sleep mode to disable downstream supplies. |
| ERR (8) | Error/power-on indication | Active-LOW output signaling internal flags (pwon, wake-up, bus/local failure) - requires 8 µs stabilization after mode change. |
| WAKE (9) | Local wake-up input | Edge-triggered (LOW→HIGH or HIGH→LOW); internal bias follows pin state to minimize leakage during idle. |
| VBAT (10) | Battery voltage input | Direct connection to vehicle battery; powers wake-up circuitry and enables cold-start diagnosis during first battery connection. |
| SPLIT (11) | Common-mode stabilization | Provides 0.5×VCC in Normal/Pwon mode to reduce EME via split termination; floats in low-power modes. |
| CANL (12) | LOW-level CAN bus line | Differential bus terminal; rated for −27 V to +40 V; short-circuit proof to battery and ground. |
| CANH (13) | HIGH-level CAN bus line | Differential bus terminal; matched dominant output voltage (±0.15 V) ensures bus symmetry and timing integrity. |
| STB (14) | Standby control input | Active-LOW; primary control for entering Standby/Sleep modes; wake-up capable even when VCC = 0 V. |
Key Features
| Feature | Design Value |
|---|---|
| Recessive bus DC voltage stabilization | SPLIT pin delivers regulated 0.5×VCC in Normal/Pwon mode to suppress common-mode steps and reduce electromagnetic emissions (EME) in partially powered networks. |
| Wake-up source recognition | Distinguishes local (WAKE pin) vs. remote (bus activity) wake-up events via dedicated internal flag - enables differentiated firmware response in sleep-aware ECUs. |
| Five-level power management | Supports Normal → Pwon/Listen-only → Standby → Go-to-sleep → Sleep transitions with <30 µA VBAT current in Sleep, preserving battery life in parked vehicles. |
| Integrated bus fault diagnostics | Detects and signals TXD dominant clamping, RXD recessive clamping, TXD-to-RXD short, bus dominant clamping, and overtemperature - all disabling transmitter to prevent network lockup. |
| Automotive transient protection | Withstands ISO 7637-2 pulse 5a (40 V load dump) and ±200 V transients on CANH/CANL/SPLIT/VBAT - eliminates need for external TVS diodes in many designs. |
Applications
| Body Control Module (BCM) | Powertrain Gateway |
|---|---|
|
Use Scenario: Centralized control of lighting, door locks, windows, and HVAC via CAN backbone. IC Role / Device Role / Timing Role: Physical layer interface between 32-bit MCU and high-speed CAN bus; handles wake-up from key fob (WAKE pin) and battery monitoring (VBAT). Use Value: Enables always-on listen-only mode for intrusion detection while drawing <30 µA, and provides bus failure diagnosis to isolate faulty nodes without disrupting gateway routing. |
Use Scenario: Aggregation and translation of CAN messages between engine, transmission, and chassis ECUs. IC Role / Device Role / Timing Role: High-integrity transceiver ensuring <255 ns TXD-to-RXD propagation delay and ±0.15 V dominant voltage matching for deterministic message forwarding. Use Value: Maintains 1 Mbit/s throughput under load dump conditions (−27 V to +40 V bus tolerance) and reports bus dominant clamping to prevent gateway lockup during short-circuit faults. |
| ADAS Domain Controller | Electric Power Steering (EPS) |
|
Use Scenario: Sensor fusion hub connecting radar, camera, and ultrasonic modules over CAN FD infrastructure. IC Role / Device Role / Timing Role: CAN physical layer supporting Pwon/Listen-only mode for diagnostic logging during ignition-off; SPLIT pin stabilizes recessive bus voltage during partial power-down. Use Value: Reduces EME by >6 dB through recessive voltage stabilization, meeting CISPR 25 Class 5 radiated emissions limits for safety-critical systems. |
Use Scenario: Real-time torque assist coordination between EPS ECU and motor driver via high-speed CAN. IC Role / Device Role / Timing Role: Fault-tolerant transceiver with overtemperature shutdown and TXD dominant timeout - prevents bus lockup during motor stall or thermal overload. Use Value: Local failure flag reporting via ERR pin allows immediate software mitigation (e.g., torque reduction) before hardware damage occurs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed CAN transceiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MCP2551-I/P | Lacks wake-up source recognition, no SPLIT pin, higher standby current (120 µA), no bus dominant clamping detection. | Suitable for cost-sensitive non-safety applications without advanced diagnostics or ultra-low-power sleep requirements. | Select when ISO 11898 compliance and basic 1 Mbit/s operation are sufficient, and diagnostic depth is not required. |
| TJA1051T/3/1J | Pin-compatible successor with improved ESD (±8 kV HBM), lower VCC min (4.5 V), integrated VIO regulator, and enhanced wake-up filtering. | Designed for next-gen automotive platforms requiring extended voltage range and tighter EMC margins. | Choose for new designs targeting ASIL-B functional safety or needing backward compatibility with TJA1041A layout. |
Compared with MCP2551-I/P and TJA1051T/3/1J, the TJA1041AT/CM,118 delivers unique value in wake-up source discrimination, recessive bus stabilization via SPLIT, and comprehensive local failure detection - making it optimal for legacy automotive ECUs where diagnostic granularity and EME control are critical but pin count and BOM cost must remain unchanged.
Availability
TJA1041AT/CM,118 is available at Aetrix Electronics and suitable for automotive body electronics, powertrain gateways, and ADAS domain controllers requiring stable component supply across extended temperature ranges (−40 °C to +150 °C) and long product lifecycles.
Supply support for TJA1041AT/CM,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in automotive-grade analog and mixed-signal ICs.
The TJA1041AT/CM,118 belongs to NXP's automotive CAN transceiver family, engineered specifically for robust, low-power, and diagnostic-rich communication in harsh vehicle environments - addressing EMI resilience, fail-safe behavior, and battery-conscious operation.
FAQ
What is the maximum data rate supported by the TJA1041AT/CM,118?
The TJA1041AT/CM,118 supports a maximum data rate of 1 Mbit/s, fully compliant with ISO 11898-2:2003 for high-speed CAN. This enables real-time communication in demanding automotive applications such as powertrain control and ADAS sensor fusion, with propagation delay from TXD to RXD specified at 40–255 ns under defined conditions.
How does the TJA1041AT/CM,118 handle undervoltage conditions on VCC or VI/O?
The TJA1041AT/CM,118 monitors VCC and VI/O continuously: if either drops below its undervoltage threshold (VCC < 3.3 V or VI/O < 1.5 V) for longer than 10 ms, the UVNOM flag sets and the device enters Sleep mode. This prevents bus disturbance and disables INH to cut downstream power - a fail-safe behavior confirmed in the TJA1041AT/CM,118 datasheet Section 7.2.1.
Can the TJA1041AT/CM,118 operate with a 3.3 V microcontroller?
Yes - the TJA1041AT/CM,118 supports VI/O from 2.8 V to 5.25 V. When supplied with 3.3 V at VI/O, its TXD, STB, and EN inputs adapt their logic thresholds, and RXD/ERR outputs scale to 3.3 V levels. This eliminates external level shifters and is explicitly validated in the TJA1041AT/CM,118 Characteristics table (Section 10, VI/O column).
What diagnostic functions are available via the ERR pin of the TJA1041AT/CM,118?
The ERR pin of the TJA1041AT/CM,118 provides active-LOW indication of five internal flags: pwon (power-on), wake-up, bus failure, local failure, and wake-up source - depending on operating mode. Each flag's availability and clearing condition is documented in Table 5 of the TJA1041AT/CM,118 datasheet, with 8 µs stabilization required after mode changes.
Does the TJA1041AT/CM,118 require external termination resistors on the CAN bus?
Yes - the TJA1041AT/CM,118 requires standard 120 Ω termination at each bus end. However, its SPLIT pin enables optional split termination (two 60 Ω resistors + capacitor to ground) to stabilize recessive common-mode voltage and reduce electromagnetic emissions. This configuration is recommended in Figure 5 of the TJA1041AT/CM,118 datasheet for EME-sensitive applications.
TJA1041AT/CM,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Transceiver
- Protocol:
- CANbus
- Number of Drivers/Receivers:
- 1/1
- Duplex:
- Half
- Receiver Hysteresis:
- 70 mV
- Data Rate:
- -
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
TJA1041AT/CM,118 FAQ
1.How can I place an order for TJA1041AT/CM,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for TJA1041AT/CM,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TJA1041AT/CM,118 reliable?
The price and inventory of TJA1041AT/CM,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TJA1041AT/CM,118 is usually 5 days.
3.What payment methods are accepted for TJA1041AT/CM,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TJA1041AT/CM,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TJA1041AT/CM,118?
TJA1041AT/CM,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TJA1041AT/CM,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TJA1041AT/CM,118?
For technical support, including TJA1041AT/CM,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TJA1041AT/CM,118 requirements.
6.How does Aetrix verify that TJA1041AT/CM,118 is sourced from the original manufacturer or authorized distributors?
All TJA1041AT/CM,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TJA1041AT/CM,118 meets industry standards.
7.What is the process for return or replacement of TJA1041AT/CM,118?
All TJA1041AT/CM,118 units undergo pre-shipment inspection (PSI). If there is an issue with TJA1041AT/CM,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TJA1041AT/CM,118 part is unused and in its original packaging.
Return procedure for TJA1041AT/CM,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TJA1041AT/CM,118 Tags
-
ATA6561-GAQW-N
Microchip Technology
-
ATA6561-GBQW-N
Microchip Technology
-
AM26LS32ACDR
Texas Instruments
-
SP485CN-L/TR
MaxLinear, Inc.
-
SP485EN-L/TR
MaxLinear, Inc.
-
SP485EEN-L/TR
MaxLinear, Inc.
-
SP485ECN-L/TR
MaxLinear, Inc.
-
THVD1400DR
Texas Instruments
-
AM26C31IDR
Texas Instruments
-
TLIN1021ADRQ1
Texas Instruments
-
MAX232IDR
Texas Instruments
-
AM26C32IDR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
