NXP Semiconductors TJA1042T/3,118

Overview

TJA1042T/3,118 from NXP Semiconductors is a high-speed CAN transceiver with Standby mode, implementing ISO 11898-2:2016 and SAE J2284-1 to J2284-5 for CAN FD fast-phase operation up to 5 Mbit/s. It features VIO pin support for direct 3.3 V microcontroller interfacing, 10 μA Standby current, ±58 V bus fault protection, and AEC-Q100 qualification for automotive body control modules.

For engineers reviewing the TJA1042T/3,118 datasheet, TJA1042T/3,118 pinout, TJA1042T/3,118 application, or TJA1042T/3,118 equivalent, this device delivers fail-safe bus wake-up capability, differential receiver hysteresis of 50–200 mV, TXD dominant time-out (0.3–5 ms), and robust EMC/ESD performance per IEC 62228-3 and SAE J2962-2 - critical for low-power automotive node design.

Technical Context

The TJA1042T/3,118 operates in Normal and Standby modes controlled by STB pin, with Standby enabling bus wake-up detection using only VIO supply. Its internal biasing on TXD and STB pins ensures defined logic states during floating conditions, and undervoltage detection on both VCC (3.5–4.5 V threshold) and VIO (1.3–2.7 V threshold) triggers safe mode transitions.

It integrates slope control for EME reduction, transmitter dominant time-out to prevent bus lockup, and bus-dominant time-out in Standby to avoid false wake-ups. The VIO-supplied low-power receiver remains active in Standby, detecting persistent bus activity longer than tfltr(wake)bus (0.5–5 μs) before asserting RXD LOW.

Key Specifications

Pinout & Package

Package: SO8 (SOT96-1), plastic small outline, 8 leads, 3.9 mm body width.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CAN transceiver applications.

Compared with TJA1042TK/3, the TJA1042T/3,118 offers easier hand-soldering and legacy board compatibility; compared with TJA1043T/3, it provides essential bus wake-up functionality for body electronics - making TJA1042T/3,118 optimal for cost-sensitive, thermally moderate automotive nodes needing reliable wake-on-CAN.

Availability

TJA1042T/3,118 is available at Aetrix Electronics and suitable for automotive body control modules, ADAS sensor hubs, electric power steering ECUs, and gateway modules requiring stable component supply across production lifecycles.

Supply support for TJA1042T/3,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on automotive, industrial, and IoT applications, delivering secure, energy-efficient, and scalable silicon solutions.

The TJA1042 product line targets automotive high-speed CAN networks requiring low-power Standby operation, fail-safe bus behavior, and AEC-Q100 reliability - specifically engineered for body electronics and distributed control nodes.

FAQ

What is the function of the VIO pin on the TJA1042T/3,118?

The VIO pin on the TJA1042T/3,118 supplies the I/O level adapter circuitry, setting logic thresholds for TXD, RXD, and STB to match the connected microcontroller's supply voltage (2.8 V to 5.5 V). It also powers the low-power differential receiver in Standby mode, enabling bus wake-up detection even when VCC is off. This eliminates level-shifter components in 3.3 V MCU designs and ensures robust signal integrity across voltage domains.

Does the TJA1042T/3,118 support CAN FD data rates up to 5 Mbit/s?

Yes, the TJA1042T/3,118 fully implements the CAN physical layer per ISO 11898-2:2016 and SAE J2284-1 to J2284-5, enabling reliable communication in the CAN FD fast phase at data rates up to 5 Mbit/s. Its propagation delay (≤250 ns) and symmetry specifications (VTXsym = 0.9VCC to 1.1VCC) are validated for this speed, and timing parameters such as tbit(RXD) and Δtrec ensure bit-level accuracy in high-speed networks.

How does the TXD dominant time-out feature protect the CAN network in the TJA1042T/3,118?

The TXD dominant time-out in the TJA1042T/3,118 disables the transmitter if TXD remains LOW longer than 0.3–5 ms, forcing the bus back to recessive state. This hardware safeguard prevents a stuck-at-dominant condition caused by MCU failure or software crash, ensuring other nodes retain bus arbitration capability. It directly supports functional safety goals by eliminating single-point failures that could halt all network communication.

What is the purpose of the STB pin on the TJA1042T/3,118, and how is it used in system design?

The STB (Standby) pin on the TJA1042T/3,118 is an active-HIGH control input that selects operating mode: LOW enables Normal mode (full transmit/receive), HIGH activates Standby mode (ultra-low-power bus monitoring). Internal pull-up to VIO ensures safe Standby if left unconnected. In system design, STB is typically driven by the MCU to coordinate sleep/wake cycles, and its transition delay (7–47 μs) is factored into wake-up latency budgets for body electronics applications.

Is the TJA1042T/3,118 qualified for automotive use, and what standards does it meet?

Yes, the TJA1042T/3,118 is AEC-Q100 Grade 1 qualified (-40 °C to +125 °C ambient), certified for automotive applications. It complies with ISO 11898-2:2016, SAE J2284-1 to J2284-5, and SAE J1939-14 for physical layer conformance. Its EMC performance meets proposed standards IEC 62228-3 and SAE J2962-2, and ESD robustness is rated at ±8 kV HBM on CANH/CANL - fulfilling Tier-1 supplier requirements for body control and chassis systems.