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NXP Semiconductors TJA1043T/1J
- Part No.:
- TJA1043T/1J
- Manufacturer:
- NXP Semiconductors
- Category:
- Drivers, Receivers, Transceivers
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
TJA1043T/1J.pdf
- Description:
- IC TRANSCEIVER HALF 1/1 14SO
- Quantity:
- Payment:
- Shipping:
Inventory:6,956
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Product details
Overview
TJA1043T/1J from NXP Semiconductors is a high-speed CAN FD transceiver compliant with ISO 11898-2:2016 and SAE J2284-1 to J2284-5, supporting data rates up to 5 Mbit/s in the fast phase. It provides differential transmit/receive capability between a CAN protocol controller and the two-wire physical bus, features VIO-level adaptability (3 V to 5 V), AEC-Q100 qualification, and operates in 12 V/24 V automotive systems.
For engineers reviewing the TJA1043T/1J datasheet, TJA1043T/1J pinout, TJA1043T/1J application, or TJA1043T/1J equivalent, key selection considerations include its dual-supply interface (VCC/VIO), ultra-low standby current (≤2 µA), integrated bus failure diagnostics, SPLIT pin for recessive level stabilization, and wake-up source recognition for robust node power management.
Technical Context
The TJA1043T/1J implements a fully isolated physical layer with loop-delay symmetry optimized for CAN FD timing integrity at 5 Mbit/s. Its architecture integrates independent VCC (4.5–5.5 V) and VIO (2.8–5.5 V) supplies, enabling direct interfacing with mixed-voltage microcontrollers while maintaining bus biasing at 0.5×VCC in Normal/Listen-only modes.
Five operating modes-Normal, Listen-only, Standby, Go-to-Sleep, and Sleep-are controlled via STB_N (active LOW) and EN pins, with diagnostic flag access through ERR_N. Internal flags (UVNOM, UVBAT, Wake, Pwon, Bus failure, Local failure, Wake-up source) support fail-safe behavior, undervoltage recovery, and remote/local wake-up pattern detection per ISO 11898-2.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Bus Data Rate | Up to 5 Mbit/s in CAN FD fast phase; enables high-bandwidth ECUs without protocol layer changes. |
| VIO Supply Range | 2.8 V to 5.5 V; allows direct connection to 3 V or 5 V microcontrollers without level shifters. |
| Standby Current | 0–2 µA; reduces system quiescent power in always-on automotive nodes. |
| ESD Robustness | ±8 kV on CANH/CANL per IEC 61000-4-2; ensures reliability in harsh automotive ESD environments. |
| Bus Fault Protection | ±58 V common-mode tolerance on CANH/CANL; withstands load dump and battery reversal events. |
| Operating Temp | −40 °C to +150 °C virtual junction temperature; supports under-hood deployment. |
| AEC-Q100 Grade | Qualified per AEC-Q100 Rev-G; meets automotive reliability and stress test requirements. |
Pinout & Package
Package: SO14 (SOT108-1), plastic small outline, 14-lead, 3.9 mm body width.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| TXD | Transmit Data Input | Asynchronous digital input from MCU; dominant timeout prevents bus lockup. |
| GND | Ground Reference | Primary supply return; connects to PCB ground plane for noise immunity and thermal dissipation. |
| VCC | Transceiver Core Supply | 4.5–5.5 V supply powering internal logic, drivers, and receivers; monitored for undervoltage (3.0–4.3 V threshold). |
| RXD | Receive Data Output | Digital output mirroring bus state; active during Normal/Listen-only modes; used for error flag polling. |
| VIO | I/O Level Adaptor Supply | 2.8–5.5 V reference setting TXD/RXD/EN/STB_N/ERR_N logic thresholds; decouples MCU voltage domain. |
| EN | Enable Control Input | Active HIGH control enabling Normal/Listen-only operation; combined with STB_N for mode selection. |
| INH | External Regulator Inhibit | Active HIGH output controlling external LDOs; floats in Sleep mode to cut auxiliary power. |
| ERR_N | Error & Power-On Flag Output | Active LOW open-drain output; multiplexes 7 internal flags (e.g., UVNOM, Wake, Bus failure) by mode. |
| WAKE | Local Wake-Up Input | Edge-triggered (LOW↔HIGH) input with internal bias; enables hardware-initiated wake from low-power states. |
| VBAT | Battery Supply Input | 4.5–40 V automotive battery rail; powers wake-up circuitry and enables zero-load bus disengagement when absent. |
| SPLIT | Common-Mode Stabilization Output | 0.5×VCC DC output in Normal/Listen-only modes; drives split termination to reduce EME on leaky buses. |
| CANL | CAN Bus Low Terminal | Differential bus line; clamped to GND during faults; rated ±58 V for transient immunity. |
| CANH | CAN Bus High Terminal | Differential bus line; clamped to VBAT during faults; rated ±58 V for transient immunity. |
| STB_N | Standby Control Input | Active LOW input selecting Standby/Go-to-Sleep/Sleep; LOW-to-HIGH transition clears UVNOM flag. |
Key Features
| Feature | Design Value |
|---|---|
| ISO 11898-2:2016 & SAE J2284-1–5 Compliance | Guarantees interoperability with CAN FD networks requiring standardized physical layer timing and fault behavior. |
| SPLIT Pin with External RC Network | Stabilizes recessive bus voltage at 0.5×VCC, reducing electromagnetic emissions in multi-node systems with leakage paths. |
| Wake-Up Source Recognition | Distinguishes local (WAKE pin) vs. remote (bus pattern) wake events via dedicated flag, enabling targeted firmware response. |
| TXD Dominant Time-Out | Disables transmitter after >4 µs dominant TXD, preventing permanent bus lockup due to MCU software hang or hardware fault. |
| Bus Line Short-Circuit Diagnosis | Detects CANH/CANL shorts to VBAT, VCC, or GND over four consecutive TXD cycles; signals via ERR_N in Normal mode. |
| Functional Behavior Under All Supply Conditions | Ensures predictable state transitions (e.g., zero-load bus disengagement when VBAT absent) without external supervision. |
Applications
| Body Control Module (BCM) | Advanced Driver Assistance Systems (ADAS) |
|---|---|
Use Scenario: Centralized vehicle subsystem managing door locks, lighting, wipers, and HVAC via CAN FD backbone. IC Role / Device Role / Timing Role: Physical layer interface translating MCU CAN controller signals to robust differential bus communication with <5 µs loop delay symmetry. Use Value: Ultra-low standby current (≤2 µA) enables always-on monitoring without draining 12 V battery; SPLIT pin stabilizes bus during sleep/wake transitions. |
Use Scenario: Radar, camera, and ultrasonic sensor fusion unit requiring deterministic 5 Mbit/s CAN FD messaging for real-time object tracking. IC Role / Device Role / Timing Role: High-integrity transceiver ensuring bit-level timing compliance for fast-phase CAN FD frames under EMI stress. Use Value: ±8 kV ESD protection and ±58 V bus tolerance maintain link integrity near high-noise powertrain components. |
| Electric Power Steering (EPS) | Infotainment Head Unit |
Use Scenario: Safety-critical steering assist system exchanging torque, angle, and fault status with vehicle domain controller. IC Role / Device Role / Timing Role: Fail-safe CAN transceiver with bus failure detection, thermal shutdown, and wake-up source identification for ASIL-B compliance. Use Value: Local failure flag (TXD-RXD short, overtemperature) enables immediate diagnostic logging; ERR_N multiplexing simplifies MCU GPIO usage. |
Use Scenario: Multimedia hub connecting navigation, audio, and telematics modules across a high-speed CAN FD network. IC Role / Device Role / Timing Role: VIO-adapted interface bridging 3.3 V application processor to 12 V vehicle bus with minimal BOM overhead. Use Value: Direct 3 V/5 V compatibility eliminates level shifters; Listen-only mode supports non-intrusive bus monitoring during firmware updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed CAN transceiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TJA1042TK/0Z | Lower VIO range (1.65–5.5 V); no SPLIT pin; identical AEC-Q100 grade and 5 Mbit/s capability. | Lacks recessive-level stabilization; suitable where board layout minimizes bus leakage or split termination is omitted. | Select when SPLIT functionality is unnecessary and lower VIO minimum (1.65 V) supports newer ultra-low-voltage MCUs. |
| MCP2562FD-H/SN | Microchip device with 5 Mbit/s CAN FD support; VIO = 2.7–5.5 V; no wake-up source flag; different pinout (SO8). | Missing UVBAT/UVNOM flag reporting and INH regulator control; requires external circuitry for battery-aware power sequencing. | Choose for cost-sensitive designs where full diagnostic flag set and integrated regulator control are not required. |
Compared with TJA1043T/1J, TJA1042TK/0Z trades SPLIT functionality for wider VIO flexibility, while MCP2562FD-H/SN offers CAN FD speed but omits critical automotive diagnostics and power management features like wake-up source recognition and INH-driven regulator control.
Availability
TJA1043T/1J is available at Aetrix Electronics and suitable for automotive body electronics, ADAS sensor fusion, electric power steering, and infotainment head units requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for TJA1043T/1J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on automotive, industrial, and IoT applications, delivering secure, energy-efficient, and highly integrated solutions.
The TJA1043T/1J belongs to NXP's third-generation high-speed CAN transceiver family, engineered specifically for automotive networks demanding ultra-low quiescent power, comprehensive diagnostics, and seamless integration with mixed-voltage microcontrollers.
FAQ
What is the maximum CAN FD data rate supported by the TJA1043T/1J?
The TJA1043T/1J supports reliable communication at up to 5 Mbit/s in the CAN FD fast phase, enabled by loop-delay symmetry timing compliant with ISO 11898-2:2016. This performance is achievable with proper PCB layout, termination, and bus length matching. The TJA1043T/1J maintains signal integrity at this rate without requiring external equalization or retiming circuits.
How does the TJA1043T/1J handle undervoltage conditions on VCC and VIO?
The TJA1043T/1J monitors VCC and VIO independently using dedicated undervoltage detection circuits. VCC undervoltage triggers the UVNOM flag when voltage drops below 3.0–4.3 V for longer than tdet(uv), forcing entry into Sleep mode. VIO undervoltage (0.8–2.5 V threshold) similarly sets UVNOM if VIO falls too low. Both flags clear only after sustained recovery beyond trec(uv), ensuring stable re-entry into Normal mode. The TJA1043T/1J remains functional during these transitions.
Can the TJA1043T/1J be used with a 3.3 V microcontroller?
Yes, the TJA1043T/1J supports direct interfacing with 3.3 V microcontrollers via its VIO pin, which accepts 2.8–5.5 V. When VIO = 3.3 V, all logic pins (TXD, RXD, EN, STB_N, ERR_N) operate at 3.3 V levels, eliminating the need for external level shifters. The TJA1043T/1J maintains full functionality-including diagnostic flag reporting and wake-up source recognition-at this voltage.
What diagnostic functions are accessible through the ERR_N pin of the TJA1043T/1J?
The ERR_N pin of the TJA1043T/1J provides multiplexed access to seven internal diagnostic flags: UVNOM (VCC/VIO undervoltage), UVBAT (battery undervoltage), Wake (local/remote wake event), Pwon (power-on), Bus failure (CANH/CANL short), Local failure (TXD-RXD short, overtemperature, etc.), and Wake-up source. Which flag appears on ERR_N depends on the current operating mode and is documented in Table 5 of the datasheet. The TJA1043T/1J uses active-LOW signaling, with LOW indicating a set flag.
Does the TJA1043T/1J support remote wake-up from Sleep mode?
Yes, the TJA1043T/1J supports remote wake-up from Sleep mode via the CAN bus using the ISO 11898-2:2016-defined wake-up pattern: dominant-recessive-dominant sequence with precise timing windows (twake(busdom), twake(busrec), tto(wake)bus). The transceiver filters spurious patterns caused by noise or clamped buses, ensuring reliable wake-up only upon valid sequences. Upon detection, the Wake flag is set and the TJA1043T/1J transitions to Standby mode, then Normal mode per STB_N/EN logic.
TJA1043T/1J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Transceiver
- Protocol:
- CANbus
- Number of Drivers/Receivers:
- 1/1
- Duplex:
- Half
- Receiver Hysteresis:
- 120 mV
- Data Rate:
- 5Mbps
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 150°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
TJA1043T/1J FAQ
1.How can I place an order for TJA1043T/1J through Aetrix?
Please submit a Request for Quotation (RFQ) for TJA1043T/1J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TJA1043T/1J reliable?
The price and inventory of TJA1043T/1J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TJA1043T/1J is usually 5 days.
3.What payment methods are accepted for TJA1043T/1J?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TJA1043T/1J transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TJA1043T/1J?
TJA1043T/1J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TJA1043T/1J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TJA1043T/1J?
For technical support, including TJA1043T/1J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TJA1043T/1J requirements.
6.How does Aetrix verify that TJA1043T/1J is sourced from the original manufacturer or authorized distributors?
All TJA1043T/1J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TJA1043T/1J meets industry standards.
7.What is the process for return or replacement of TJA1043T/1J?
All TJA1043T/1J units undergo pre-shipment inspection (PSI). If there is an issue with TJA1043T/1J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TJA1043T/1J part is unused and in its original packaging.
Return procedure for TJA1043T/1J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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