NXP Semiconductors TJA1443ATK/0Z
- Part No.:
- TJA1443ATK/0Z
- Manufacturer:
- NXP Semiconductors
- Category:
- Drivers, Receivers, Transceivers
- Package:
- 14-VDFN Exposed Pad
- Datasheet:
-
TJA1443ATK/0Z.pdf
- Description:
- IC TRANSCEIVER HALF 1/1 14HVSON
- Quantity:
- Payment:

- Shipping:

Inventory:308
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Product details
Overview
TJA1443ATK/0Z from NXP Semiconductors is a high-speed CAN FD transceiver implementing ISO 11898-2:2016 and SAE J2284-1 to J2284-5, supporting data rates up to 5 Mbit/s, AEC-Q100 Grade 1 qualification, and VIO interface for 3.3 V–5 V microcontrollers in automotive body control modules.
For engineers reviewing the TJA1443ATK/0Z datasheet, TJA1443ATK/0Z pinout, TJA1443ATK/0Z application, or TJA1443ATK/0Z equivalent, key selection criteria include its HVSON14 package footprint, bus wake-up pattern filter time (0.5–1.8 μs), Listen-only mode for node diagnosis, and fail-safe undervoltage behavior across VBAT/VCC/VIO rails.
Technical Context
The TJA1443ATK/0Z integrates dual state machines - system and CAN - enabling gap-free operation across supply voltage transitions and predictable mode switching between Normal, Standby, Sleep, Listen-only, and Off states. It uses VIO-supplied logic levels and VBAT-powered wake-up receiver to maintain bus monitoring while VCC/VIO are shut down.
Its CAN physical layer supports Classical CAN and CAN FD fast-phase signaling with SIC capability per CiA 601-4:2019, differential bus biasing at VCC/2 in active modes, and high-ohmic bus disengagement below VBAT undervoltage threshold (4.0–4.5 V). Local failure detection includes TXD dominant timeout, TXD–RXD short-circuit handling, bus dominant clamping, and overtemperature shutdown.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | Up to 5 Mbit/s CAN FD - enables full utilization of CAN FD payload bandwidth in ECU gateway and ADAS domain controllers. |
| VBAT supply range | 4.5 V to 28 V - supports wide automotive battery voltage variation including cold-crank conditions. |
| IBAT in Sleep mode | 13–20 µA - allows entire ECU node to enter ultra-low-power state while retaining bus wake-up capability. |
| Wake-up pattern filter | 0.5 µs to 1.8 µs - meets ISO 11898-2:2016 requirements for reliable remote wake-up under noise-prone bus conditions. |
| ESD protection | ±8 kV IEC 61000-4-2 on CANH/CANL - ensures robustness against electrostatic discharge in assembly and service environments. |
| Operating temperature | −40 °C to +150 °C - qualified per AEC-Q100 Grade 1 for under-hood and powertrain applications. |
| VIO range | 2.95 V to 5.5 V - enables direct interfacing with 3.3 V or 5 V microcontrollers without level-shifting circuitry. |
Pinout & Package
HVSON14 package (3.0 mm × 4.5 mm × 0.85 mm), leadless thermal-enhanced outline with exposed center pad for improved thermal dissipation and AOI compatibility.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TXD | Digital input | Receives transmit data from CAN controller; initiates bus transmission when driven LOW in Normal mode. |
| RXD | Digital output | Delivers received bus data to controller; held LOW during wake-up event for source recognition. |
| CANH / CANL | Analog I/O | Differential bus interface; biased to VCC/2 in Normal/Listen-only modes; high-ohmic in Off mode. |
| VBAT | Power supply | Main battery rail input; powers wake-up receiver independently - enables wake-up even with VCC/VIO off. |
| VCC | Power supply | 5 V logic supply; undervoltage detection (4.0–4.5 V) triggers safe transition to Sleep/Standby. |
| VIO | Power supply | I/O voltage reference; sets logic levels for TXD/RXD/STB_N/EN/ERR_N; undervoltage hysteresis = 50 mV. |
| STB_N | Digital input | Active-LOW standby control; rising edge wakes device from Sleep to Standby if VIO valid. |
| EN | Digital input | Enables Normal (HIGH) or Listen-only (LOW) mode; used with STB_N to select functional state. |
| ERR_N | Digital output | Active-LOW flag output; indicates Pwon, Wake, Wake-up source, or Local failure per mode-dependent mapping. |
| WAKE | Analog input | Local wake-up trigger; detects stable HIGH/LOW transitions; internal bias follows logic state after delay. |
| INH | Analog output | Regulator enable signal; HIGH in Normal/Standby/Listen-only; high-ohmic in Sleep/Off to disable external supplies. |
| GND | Ground | Reference for all supplies and signals; die ground connected to pin and exposed pad - pad must be soldered. |
| n.c. | Not connected | No internal connection; must remain unconnected on PCB. |
Key Features
| Feature | Design Value |
|---|---|
| Fail-safe undervoltage response | Defined behavior across VBAT/VCC/VIO thresholds - prevents undefined states during brown-out; bus disengages at VBAT < 4.0 V. |
| Multi-source wake-up | Supports local (WAKE pin), remote (CAN bus pattern), and power-on (Pwon) wake-up - enables flexible low-power architecture design. |
| Listen-only diagnostic mode | Receiver active + transmitter disabled - allows non-intrusive bus monitoring and fault isolation without affecting network traffic. |
| Integrated local failure detection | Four independent diagnostics: TXD dominant timeout, TXD–RXD short, bus dominant clamp, and overtemperature - reduces need for external supervision. |
| Signal Improvement Capability (SIC) | Complies with CiA 601-4:2019 - improves bit timing margin and noise immunity in CAN FD fast-phase communication. |
Applications
| Body Control Module (BCM) | Advanced Driver Assistance Systems (ADAS) Domain Controller |
|---|---|
|
Use Scenario: Centralized vehicle body electronics managing door locks, lighting, window lifts, and climate via CAN FD backbone. IC Role / Device Role / Timing Role: Physical layer interface between MCU and CAN FD bus; provides Listen-only mode for runtime diagnostics and fail-safe bus disengagement during undervoltage. Use Value: Enables retrofit into legacy Classical CAN designs due to pin compatibility with TJA1043; reduces BOM count by eliminating external level shifters via VIO support. |
Use Scenario: High-bandwidth sensor fusion hub aggregating radar, camera, and ultrasonic data using CAN FD for deterministic latency. IC Role / Device Role / Timing Role: High-speed transceiver with 5 Mbit/s capability and SIC compliance; ensures signal integrity across long harness runs in noisy engine bay environments. Use Value: Ultra-low Sleep current (13–20 µA) allows continuous bus monitoring without compromising ECU sleep budget; wake-up pattern filter rejects false triggers from EMI. |
| Electric Powertrain Inverter Control | Commercial Vehicle Telematics Gateway |
|
Use Scenario: Real-time torque and thermal management communication between inverter MCU and vehicle controller over ruggedized CAN FD link. IC Role / Device Role / Timing Role: Robust physical layer with ±36 V bus fault tolerance and 150 °C junction rating; supports operation near high-power switching stages. Use Value: Overtemperature shutdown and bus dominant clamping detection prevent cascading failures during inverter overcurrent events; ERR_N flag enables rapid fault logging. |
Use Scenario: Fleet telematics unit collecting GPS, engine data, and driver behavior metrics across mixed Classical CAN and CAN FD subnets. IC Role / Device Role / Timing Role: Interoperable transceiver compliant with ISO 11898-2:2016 and SAE J1939-14; bridges legacy and next-gen networks without protocol translation. Use Value: Dual wake-up sources (bus + WAKE pin) allow coordinated sleep/wake across multiple ECUs; INH output controls auxiliary power domains to minimize quiescent draw. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed CAN FD transceiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TJA1043T/0Z | Classical CAN only (1 Mbit/s max); no CAN FD support; identical SO14/HVSON14 pinout and VIO interface. | Limited to legacy networks; lacks SIC, Listen-only mode, and 5 Mbit/s capability required for new ADAS or powertrain designs. | Select TJA1043T/0Z only for cost-sensitive Classical CAN upgrades where CAN FD bandwidth is unnecessary. |
| TJA1442ATK/0Z | Same family, but lacks VIO pin - fixed 5 V I/O logic; no 3.3 V microcontroller compatibility; otherwise matches TJA1443ATK/0Z specs. | Requires 5 V MCU interface; unsuitable for mixed-voltage systems using 3.3 V controllers without level shifters. | Choose TJA1442ATK/0Z only when MCU I/O is strictly 5 V and board space precludes adding level-shifting components. |
Compared with TJA1043T/0Z and TJA1442ATK/0Z, the TJA1443ATK/0Z uniquely delivers CAN FD at 5 Mbit/s with 3.3 V–5 V I/O flexibility and integrated local diagnostics - making it the only option among the three that supports future-proof, low-power, multi-voltage automotive architectures without redesign.
Availability
TJA1443ATK/0Z is available at Aetrix Electronics and suitable for automotive body control modules, ADAS domain controllers, and electric powertrain inverters requiring stable component supply, AEC-Q100 compliance, and long-term lifecycle support.
Supply support for TJA1443ATK/0Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on automotive, industrial, IoT, and communication infrastructure solutions, with deep expertise in secure connectivity and embedded processing.
The TJA1443ATK/0Z belongs to NXP's TJx144x CAN FD transceiver family, designed specifically for energy-efficient, fail-safe automotive networking - emphasizing ultra-low Sleep current, multi-source wake-up, and robust diagnostics for next-generation E/E architectures.
FAQ
What is the maximum data rate supported by the TJA1443ATK/0Z?
The TJA1443ATK/0Z supports CAN FD data rates up to 5 Mbit/s, as specified in ISO 11898-2:2016 and verified in its Quick Reference Data table. This enables high-throughput communication for applications like ADAS sensor fusion and powertrain control, where Classical CAN's 1 Mbit/s limit is insufficient. The TJA1443ATK/0Z achieves this while maintaining backward compatibility with Classical CAN nodes on the same bus.
Does the TJA1443ATK/0Z support 3.3 V microcontrollers?
Yes, the TJA1443ATK/0Z supports 3.3 V microcontrollers via its dedicated VIO pin, which accepts 2.95 V to 5.5 V. This adjusts logic levels on TXD, RXD, STB_N, EN, and ERR_N to match the MCU's I/O voltage - eliminating external level shifters. The TJA1443ATK/0Z datasheet confirms VIO undervoltage detection thresholds (2.65–2.95 V) and hysteresis (50 mV) ensure reliable interfacing across voltage tolerances.
How does the TJA1443ATK/0Z handle undervoltage conditions?
The TJA1443ATK/0Z implements independent undervoltage detection on VBAT, VCC, and VIO pins, with defined thresholds (e.g., Vuvd(VBAT) = 4.0–4.5 V) and hysteresis (50 mV). Below threshold, it transitions predictably to Sleep or Off mode and disengages the bus (high-ohmic). This prevents undefined states during brown-out and ensures fail-safe behavior - critical for automotive safety-critical networks.
What wake-up sources does the TJA1443ATK/0Z support?
The TJA1443ATK/0Z supports three wake-up sources: remote (CAN bus wake-up pattern per ISO 11898-2:2016), local (WAKE pin transition), and power-on (Pwon flag). Its wake-up pattern filter (0.5–1.8 μs) meets CAN FD timing requirements, and the VBAT-powered wake-up receiver remains active even when VCC/VIO are shut down - enabling true zero-power monitoring of the bus.
Is the TJA1443ATK/0Z pin-compatible with the TJA1043?
Yes, the TJA1443ATK/0Z is explicitly designed as a pin-compatible replacement for the TJA1043, as stated in its General Description: "intended as a simple replacement… offers pin compatibility and is designed to avoid changes to hardware and software design." Both share identical HVSON14 (SOT1086-2) and SO14 (SOT108-1) footprints, pin functions, and electrical interface - enabling drop-in upgrade to CAN FD without PCB revision.
TJA1443ATK/0Z Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 14-VDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Transceiver
- Protocol:
- CANbus
- Number of Drivers/Receivers:
- 1/1
- Duplex:
- Half
- Receiver Hysteresis:
- 50 mV
- Data Rate:
- 5Mbps
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-HVSON (3x4.5)
TJA1443ATK/0Z FAQ
1.How can I place an order for TJA1443ATK/0Z through Aetrix?
Please submit a Request for Quotation (RFQ) for TJA1443ATK/0Z on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TJA1443ATK/0Z reliable?
The price and inventory of TJA1443ATK/0Z are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TJA1443ATK/0Z is usually 5 days.
3.What payment methods are accepted for TJA1443ATK/0Z?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TJA1443ATK/0Z transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TJA1443ATK/0Z?
TJA1443ATK/0Z orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TJA1443ATK/0Z order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TJA1443ATK/0Z?
For technical support, including TJA1443ATK/0Z datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TJA1443ATK/0Z requirements.
6.How does Aetrix verify that TJA1443ATK/0Z is sourced from the original manufacturer or authorized distributors?
All TJA1443ATK/0Z products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TJA1443ATK/0Z meets industry standards.
7.What is the process for return or replacement of TJA1443ATK/0Z?
All TJA1443ATK/0Z units undergo pre-shipment inspection (PSI). If there is an issue with TJA1443ATK/0Z, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TJA1443ATK/0Z part is unused and in its original packaging.
Return procedure for TJA1443ATK/0Z:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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