Texas Instruments TLC0820ACFN
- Part No.:
- TLC0820ACFN
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 20-LCC (J-Lead)
- Datasheet:
-
TLC0820ACFN.pdf
- Description:
- IC ADC 8BIT FLASH 20PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:1,978
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TLC0820ACFN from Texas Instruments is an Advanced LinCMOS™ 8-bit analog-to-digital converter using modified flash architecture, featuring 1.18 µs conversion time, ±1 LSB total unadjusted error, differential reference inputs, and parallel TTL-compatible microprocessor interface. It operates from a single 5-V supply and integrates on-chip track-and-hold for continuous analog signals up to 100 mV/µs slew rate - used in high-speed data acquisition systems for industrial instrumentation and motor control feedback loops.
For engineers reviewing the TLC0820ACFN datasheet, TLC0820ACFN pinout, TLC0820ACFN application, or TLC0820ACFN equivalent, key selection criteria include its read/write dual-mode operation (MODE-selectable), overflow flag (OFLW) for cascaded resolution extension, interrupt-driven timing (INT), and compatibility with legacy 8-bit microcontrollers via WR/RDY and RD control signals.
Technical Context
The TLC0820ACFN implements a two-stage modified flash architecture: first, a 4-bit flash ADC digitizes the MSBs; then a precision 4-bit DAC generates a reconstructed analog voltage, whose difference from the input is measured by a second 4-bit flash ADC for the LSBs. This architecture achieves full 8-bit resolution without external clocking or sampling components.
It supports two distinct interface modes: Read Mode (MODE = low), where RD initiates conversion and WR/RDY acts as a ready output; and Write-Read Mode (MODE = high), where WR/RDY initiates conversion and INT signals completion after ~800 ns. Both modes use CS for device selection and provide 3-state digital outputs (D0–D7) with TTL-level compatibility.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 8-bit - delivers 256 discrete digital codes over full-scale input range |
| Conversion Time | 1.18 µs - enables sampling rates up to ~847 kSPS in burst mode |
| Total Unadjusted Error | ±1 LSB - guarantees monotonicity and eliminates need for system-level calibration |
| Reference Inputs | Differential (REF+, REF–) - supports ratiometric measurement and flexible full-scale adjustment |
| Supply Voltage | Single 5 V (4.5–5.25 V) - simplifies power design and eliminates dual-rail requirements |
| Track-and-Hold | On-chip, 100-ns aperture - captures fast transients without external sample-hold circuitry |
| Output Interface | Parallel, 3-state TTL-compatible - directly interfaces to 8080/8085/Z80-style buses without level shifters |
Pinout & Package
PLCC-20 (FN package), 0.9-inch square body, 1.27 mm lead pitch, J-lead configuration with pin 1 index corner. RoHS-compliant, obsolete but available through authorized channels.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ANLG IN (Pin 1) | Analog input | Accepts single-ended or pseudo-differential analog signal within –0.1 V to VCC+0.1 V range |
| REF+ (Pin 12), REF– (Pin 11) | Differential reference inputs | Define full-scale range; common-mode voltage bounded by GND and VCC |
| CS (Pin 13), RD (Pin 8), WR/RDY (Pin 6) | Microprocessor control | Enable device selection (CS), initiate read (RD), and trigger conversion or indicate ready (WR/RDY) |
| MODE (Pin 7) | Interface mode select | Low = Read Mode (RD starts conversion); High = Write-Read Mode (WR starts conversion) |
| D0–D7 (Pins 2–5, 14–17) | Parallel digital outputs | 3-state TTL outputs delivering 8-bit result; active only when CS low and RD asserted (or WR/RDY deasserted in Read Mode) |
| INT (Pin 9), OFLW (Pin 18) | Status flags | INT signals conversion completion (~800 ns after WR↑); OFLW asserts low if input exceeds VREF+, enabling cascading |
| GND (Pin 10), VCC (Pin 20) | Power | Single-supply operation; decoupling required at VCC/GND per layout guidelines |
| NC (Pin 19) | No internal connection | Not bonded; must remain unconnected on PCB |
Key Features
| Feature | Design Value |
|---|---|
| Modified flash conversion architecture | Combines speed of flash with reduced component count vs. full 8-bit flash; achieves 1.18 µs conversion with low power |
| On-chip track-and-hold | 100-ns sample window supports analog signals with up to 100 mV/µs slew rate - no external TH circuit needed |
| Dual interface modes | Hardware-selectable Read Mode (RD-triggered) or Write-Read Mode (WR-triggered) - adapts to diverse MCU bus protocols |
| Overflow flag (OFLW) | Enables cascading two TLC0820ACFN devices for 9-bit resolution (Figure 6), extending dynamic range without redesign |
| TTL-compatible 3-state outputs | Direct connection to 8-bit data buses (e.g., 8085, Z80) without pull-ups or level translators; reduces BOM and layout complexity |
Applications
| Industrial Data Acquisition | Motor Control Feedback |
|---|---|
Use Scenario: Real-time monitoring of temperature, pressure, and current sensors in PLC I/O modules. IC Role / Device Role / Timing Role: Primary ADC capturing analog sensor outputs at ≤800 kSPS with deterministic latency (≤2.5 µs max in Read Mode). Use Value: Eliminates external sample-hold and clock generation, reducing board area and jitter-sensitive timing paths. | Use Scenario: Closed-loop current sensing in servo drives using shunt resistor voltage feedback. IC Role / Device Role / Timing Role: High-speed digitization of motor phase currents synchronized to PWM cycles via RD strobe. Use Value: 100 mV/µs slew-rate tracking ensures accurate capture of fast current transients during switching events. |
| Legacy Microcontroller Interfaces | Multi-Channel Resolution Extension |
Use Scenario: Upgrading 8-bit embedded systems (e.g., 8051-based controllers) with minimal firmware changes. IC Role / Device Role / Timing Role: Drop-in ADC replacement supporting both RD-only and WR/RDY-initiated protocols via MODE pin. Use Value: Pin-compatible with National Semiconductor ADC0820C/CC and Analog Devices AD7820K/B/T - preserves existing PCB layout. | Use Scenario: Enhancing resolution in test equipment requiring >8-bit accuracy without switching to 10-bit+ converters. IC Role / Device Role / Timing Role: Master-slave cascaded pair using OFLW and shared RD/CS to generate 9-bit output (MSB from master, LSB from slave). Use Value: Achieves 9-bit effective resolution using two identical TLC0820ACFN units - avoids costly redesign for higher-resolution ICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit parallel ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADC0820CCN | Same pinout, identical electrical specs, but fabricated in NMOS (not LinCMOS); higher supply current (20 mA vs. 13 mA typ) | Limited to 0°C to 70°C; lacks LinCMOS low-power advantage and improved noise immunity | Select when legacy NMOS compatibility is mandatory and power budget allows higher ICC |
| AD7820KN | Same 20-pin PDIP footprint; uses successive approximation (not flash), resulting in 15 µs conversion time (vs. 1.18 µs) | Lower power (5 mW vs. 65 mW), but unsuitable for high-speed sampling; no OFLW or cascading support | Select for low-power, lower-speed applications where timing determinism is less critical than energy efficiency |
Compared with ADC0820CCN and AD7820KN, the TLC0820ACFN delivers superior speed and integrated track-and-hold in a LinCMOS process, making it optimal for real-time control loops - whereas ADC0820CCN trades power for legacy equivalence, and AD7820KN prioritizes low power over throughput.
Availability
TLC0820ACFN is available at Aetrix Electronics and suitable for industrial instrumentation, motor control feedback, and legacy microcontroller interface applications requiring stable component supply and long-term obsolescence management.
Supply support for TLC0820ACFN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in precision data conversion and industrial-grade IC design.
The TLC0820A family was developed for high-speed, low-latency 8-bit digitization in resource-constrained industrial and control systems - emphasizing interface flexibility, on-chip integration, and compatibility with legacy 8-bit microprocessors.
FAQ
What is the maximum analog input slew rate supported by the TLC0820ACFN without external track-and-hold?
The TLC0820ACFN integrates an on-chip track-and-hold circuit with a 100-ns sample window, enabling accurate digitization of analog signals with slew rates up to 100 mV/µs. This specification is verified across the full operating temperature range (0°C to 70°C) and eliminates the need for external sampling components in most high-speed industrial sensing applications using the TLC0820ACFN.
Does the TLC0820ACFN require an external clock or oscillator to operate?
No, the TLC0820ACFN does not require an external clock or oscillator. Its modified flash architecture and internal timing logic enable autonomous conversion initiation and completion using only control signals (RD, WR/RDY, CS, and MODE). This self-timed operation simplifies system design and removes clock distribution and jitter concerns - a confirmed feature of the TLC0820ACFN per its datasheet SLAS064A.
How does the MODE pin affect the interface timing behavior of the TLC0820ACFN?
The MODE pin selects between two distinct interface protocols: when MODE is low, the TLC0820ACFN operates in Read Mode (RD initiates conversion, WR/RDY acts as ready output); when MODE is high, it enters Write-Read Mode (WR/RDY initiates conversion, INT signals completion after ~800 ns). These modes are electrically and functionally separate - the TLC0820ACFN's timing diagrams (Figures 1–4) confirm mode-dependent delays including td(int), ta(R1), and td(WR).
Can the TLC0820ACFN be used to achieve more than 8-bit resolution?
Yes, the TLC0820ACFN includes an overflow flag (OFLW) specifically designed to cascade multiple units. As shown in Figure 6 of the datasheet, two TLC0820ACFN devices can be configured in master-slave arrangement to deliver 9-bit resolution - the master's OFLW controls the slave's conversion trigger, and results are combined in software or logic. This capability is intrinsic to the TLC0820ACFN's architecture and requires no external components beyond standard interconnect.
Is the TLC0820ACFN pin-compatible with other industry-standard 8-bit ADCs?
Yes, the TLC0820ACFN is pin-compatible with National Semiconductor's ADC0820C/CC and Analog Devices' AD7820K/B/T in the 20-pin PDIP (N) and PLCC (FN) packages. The pin functions, electrical characteristics, and timing behavior align sufficiently to allow direct substitution in existing designs - a claim explicitly stated in the "TLC0820A Is Direct Replacement" section of the TLC0820ACFN datasheet SLAS064A.
TLC0820ACFN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- LinCMOS™
- Package/Case:
- 20-LCC (J-Lead)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Number of Bits:
- 8
- Sampling Rate (Per Second):
- 392k
- Number of Inputs:
- 1
- Input Type:
- Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Flash
- Reference Type:
- External
- Voltage - Supply, Analog:
- 4.5V ~ 8V
- Voltage - Supply, Digital:
- 4.5V ~ 8V
- Features:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 20-PLCC (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
TLC0820ACFN FAQ
1.How can I place an order for TLC0820ACFN through Aetrix?
Please submit a Request for Quotation (RFQ) for TLC0820ACFN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TLC0820ACFN reliable?
The price and inventory of TLC0820ACFN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TLC0820ACFN is usually 5 days.
3.What payment methods are accepted for TLC0820ACFN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TLC0820ACFN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TLC0820ACFN?
TLC0820ACFN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TLC0820ACFN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TLC0820ACFN?
For technical support, including TLC0820ACFN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TLC0820ACFN requirements.
6.How does Aetrix verify that TLC0820ACFN is sourced from the original manufacturer or authorized distributors?
All TLC0820ACFN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TLC0820ACFN meets industry standards.
7.What is the process for return or replacement of TLC0820ACFN?
All TLC0820ACFN units undergo pre-shipment inspection (PSI). If there is an issue with TLC0820ACFN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TLC0820ACFN part is unused and in its original packaging.
Return procedure for TLC0820ACFN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TLC0820ACFN Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

