Texas Instruments TLE2072AIP
- Part No.:
- TLE2072AIP
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
TLE2072AIP.pdf
- Description:
- IC OPAMP JFET 2 CIRCUIT 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,190
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Product details
Overview
TLE2072AIP from Texas Instruments is a dual-channel, JFET-input operational amplifier optimized for high-voltage, low-noise, high-speed precision applications. It delivers ±3.5 mV max input offset voltage (25°C), 10.6 MHz unity-gain bandwidth, 32 V/μs slew rate, and 17 nV/√Hz input voltage noise at 1 kHz - enabling accurate signal conditioning in oscilloscope front-ends and electricity metering circuits.
For engineers reviewing the TLE2072AIP datasheet, TLE2072AIP pinout, TLE2072AIP application, or TLE2072AIP equivalent, this device is selected for designs requiring rail-to-rail input operation, ±19 V supply capability, low bias current (±15 pA), and stable unity-gain performance in dual-amplifier configurations.
Technical Context
The TLE2072AIP implements a JFET-input stage with on-chip Zener trimming for DC precision, supporting differential input voltages up to the supply rails. Its internal compensation ensures unity-gain stability while maintaining 10.6 MHz bandwidth and 56° phase margin with 2 kΩ load and 25 pF capacitive load.
It operates across −40°C to +85°C with supply ranges from ±2.25 V to ±19 V, delivering 13.5 V maximum positive output swing and −13.5 V negative swing at ±15 V supplies with 2 mA load - critical for wide-dynamic-range data acquisition stages.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | Dual - enables matched-pair signal processing in instrumentation and sensor interfaces without inter-device matching drift. |
| Supply Voltage Range | ±2.25 V to ±19 V - supports high-voltage industrial sensing and AC drive monitoring without external level-shifting. |
| Input Offset Voltage (max) | 3.5 mV at 25°C - ensures sub-0.1% gain error in 10-bit+ precision measurement paths with minimal calibration overhead. |
| Unity-Gain Bandwidth | 10.6 MHz - allows stable closed-loop operation up to 100 kHz with ≥60 dB open-loop gain for anti-aliasing filter design. |
| Slew Rate | 32 V/μs - sustains full-scale 10 Vpp signals at ≥3 MHz without distortion in fast-settling data acquisition systems. |
| Input Voltage Noise | 17 nV/√Hz at 1 kHz - preserves SNR in low-level transducer amplification (e.g., shunt-based current sensing) below 100 kHz. |
| Input Bias Current | ±15 pA typical - minimizes voltage error across high-impedance sources (e.g., piezoelectric sensors, pH electrodes). |
Pinout & Package
Package: PDIP-8 (Plastic Dual In-line Package), 9.59 mm × 7.94 mm, through-hole mountable with industry-standard 0.3-inch row spacing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Inverting Input (Channel 1) | High-impedance JFET node accepting differential signal reference; supports common-mode range to supply rails. |
| 2 | Non-inverting Input (Channel 1) | High-impedance JFET node for signal source connection; matched to Pin 1 for CMRR optimization. |
| 3 | Output (Channel 1) | Class-AB output stage capable of ±65 mA short-circuit current and ±13.5 V swing into 2 kΩ at ±15 V supplies. |
| 4 | V– (Negative Supply) | Power rail connection for dual-supply operation; must be decoupled locally to minimize PSRR degradation. |
| 5 | Non-inverting Input (Channel 2) | Independent high-Z input for second signal path; electrically isolated from Channel 1 except via shared supply pins. |
| 6 | Inverting Input (Channel 2) | Matched to Pin 5; enables differential configuration or independent single-ended amplification per channel. |
| 7 | Output (Channel 2) | Identical output drive capability to Pin 3; supports simultaneous dual-channel signal conditioning without crosstalk >100 dB. |
| 8 | V+ (Positive Supply) | Power rail connection; supplies both channels; requires local 0.1 μF ceramic decoupling adjacent to pin. |
Key Features
| Feature | Design Value |
|---|---|
| Low input offset voltage (3.5 mV max) | Reduces zero-point calibration frequency in portable DMMs and battery-powered sensor nodes. |
| Rail-to-rail input operation | Accepts signals within 0.9 V of either supply rail - simplifies interface to unbuffered ADC drivers and high-side current monitors. |
| 17 nV/√Hz input voltage noise | Maintains >80 dB SNR for 100 mVpp signals up to 10 kHz in oscilloscope vertical amplifiers and power analyzer inputs. |
| ±19 V supply capability | Eliminates need for external charge pumps or boost regulators in AC charging station voltage monitoring circuits. |
| Unity-gain stable architecture | Enables direct use in buffer, active filter, and transimpedance configurations without external compensation components. |
Applications
| AC Drive Power Stage Module | Oscilloscopes & Digitizers |
|---|---|
Use Scenario: Monitoring motor phase currents and DC-link voltage in variable-frequency drives using shunt resistors and voltage dividers. IC Role / Device Role / Timing Role: Dual-channel signal conditioner amplifying low-level shunt voltage (Ch1) and scaled DC-link voltage (Ch2) simultaneously. Use Value: ±19 V supply tolerance enables direct connection to 380 VAC rectified rails; 32 V/μs slew rate preserves transient fidelity during IGBT switching events. | Use Scenario: Front-end amplification in 100 MHz-class digital storage oscilloscopes before ADC sampling. IC Role / Device Role / Timing Role: High-fidelity, low-noise gain stage providing programmable attenuation and offset control per channel. Use Value: 17 nV/√Hz noise floor and 10.6 MHz bandwidth support 8-bit ENOB at 10 MHz input; dual-channel matching reduces channel-to-channel skew. |
| Electricity Meter | Digital Multimeter (DMM) |
Use Scenario: Isolated current and voltage sensing in Class 0.2 polyphase energy meters compliant with IEC 62053-21. IC Role / Device Role / Timing Role: Precision amplifier for Rogowski coil and resistor-divider outputs feeding metrology ADCs. Use Value: 3.5 mV max VIO contributes <0.035% gain error at 10 V full scale; ±15 pA IIB prevents drift in high-Z voltage divider networks. | Use Scenario: Autoranging analog front-end in handheld 4½-digit DMMs measuring AC/DC voltage, current, and resistance. IC Role / Device Role / Timing Role: Dual op-amp implementing precision integrator (Ch1) and reference buffer (Ch2) in dual-slope conversion architecture. Use Value: Unity-gain stability eliminates external compensation; low 1/f noise ensures <1 μVpp residual in 10 Hz–10 kHz integration windows. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual JFET-input op-amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TL072CP | Higher 6 mV max VIO, 12.5 V/μs slew rate, 18 nV/√Hz noise at 1 kHz | Lower precision and speed; suitable for non-critical audio and general-purpose amplification | Select when cost sensitivity outweighs noise/speed requirements and ±19 V operation is not needed. |
| OPA2134PA | Lower 2 mV max VIO, 20 V/μs slew rate, 8 nV/√Hz noise, but limited to ±18 V max supply | Better noise and offset, but narrower supply range constrains use in high-voltage industrial monitoring | Prefer for battery-powered portable test equipment where ultra-low noise dominates over supply headroom. |
Compared with TL072CP and OPA2134PA, the TLE2072AIP uniquely balances ±19 V operation, 32 V/μs slew rate, and 17 nV/√Hz noise - making it optimal for high-dynamic-range industrial measurement where rail extension and transient fidelity are jointly critical.
Availability
TLE2072AIP is available at Aetrix Electronics and suitable for AC drive power stage modules, oscilloscope front-ends, and electricity metering systems requiring stable component supply across extended temperature and voltage ranges.
Supply support for TLE2072AIP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing solutions, with decades of heritage in precision op-amp design and manufacturing.
The TLE207x family was engineered for high-voltage, low-noise signal conditioning in industrial test equipment, energy infrastructure, and aerospace-grade instrumentation - emphasizing DC accuracy, AC bandwidth, and rugged supply tolerance.
FAQ
What is the maximum supply voltage rating for the TLE2072AIP?
The TLE2072AIP supports a total supply voltage (VCC+ – VCC−) up to 38 V, enabling operation from ±2.25 V to ±19 V. This rating is confirmed in Section 6.1 Absolute Maximum Ratings of the TI datasheet SLOS181D, and allows direct interfacing with rectified 380 VAC bus monitoring circuits after appropriate scaling.
Does the TLE2072AIP support rail-to-rail input operation?
Yes, the TLE2072AIP accepts common-mode input voltages extending to within 0.9 V of either supply rail (e.g., −10.9 V to +14.1 V at ±15 V supplies). This is explicitly specified in Table 6.2 Recommended Operating Conditions and verified in electrical characteristics tables for VICR across temperature and supply conditions.
What is the input bias current specification for the TLE2072AIP?
The TLE2072AIP exhibits ±15 pA typical input bias current at 25°C, with a maximum of ±175 pA across the full −40°C to +85°C operating range. This value is documented in Tables 6.3 (TLE2072C) and 6.7 (TLE2072I) under IIB, confirming its suitability for high-impedance sensor interfaces like piezoelectric accelerometers and pH probes.
Is the TLE2072AIP unity-gain stable?
Yes, the TLE2072AIP is internally compensated for unity-gain stability, with a measured phase margin of 56° at unity gain under standard test conditions (VI = 10 mV, CL = 25 pF, RL = 2 kΩ). This is specified in Tables 6.4 and 6.8 under φm, allowing direct use in voltage followers and active filters without external compensation.
What package type is used for the TLE2072AIP?
The TLE2072AIP uses an 8-pin Plastic Dual In-line Package (PDIP), designated as "P" in TI's packaging nomenclature. Its dimensions are 9.59 mm × 7.94 mm, with 0.3-inch lead spacing, and it is rated for operation from −40°C to +85°C (I-suffix temperature grade).
TLE2072AIP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Bulk
- Product Status:
- Active
- Amplifier Type:
- J-FET
- Number of Circuits:
- 2
- Output Type:
- -
- Slew Rate:
- 45V/µs
- Gain Bandwidth Product:
- 10 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 1 pA
- Voltage - Input Offset:
- 300 µV
- Current - Supply:
- 3.1mA (x2 Channels)
- Current - Output / Channel:
- 48 mA
- Voltage - Supply Span (Min):
- 4.5 V
- Voltage - Supply Span (Max):
- 38 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
TLE2072AIP FAQ
1.How can I place an order for TLE2072AIP through Aetrix?
Please submit a Request for Quotation (RFQ) for TLE2072AIP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TLE2072AIP reliable?
The price and inventory of TLE2072AIP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TLE2072AIP is usually 5 days.
3.What payment methods are accepted for TLE2072AIP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TLE2072AIP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TLE2072AIP?
TLE2072AIP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TLE2072AIP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TLE2072AIP?
For technical support, including TLE2072AIP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TLE2072AIP requirements.
6.How does Aetrix verify that TLE2072AIP is sourced from the original manufacturer or authorized distributors?
All TLE2072AIP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TLE2072AIP meets industry standards.
7.What is the process for return or replacement of TLE2072AIP?
All TLE2072AIP units undergo pre-shipment inspection (PSI). If there is an issue with TLE2072AIP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TLE2072AIP part is unused and in its original packaging.
Return procedure for TLE2072AIP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TLE2072AIP Tags

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LM358DT
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LM358DR
Texas Instruments

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Microchip Technology

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MCP6006UT-E/OT
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LM358P
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