Toshiba Semiconductor and Storage TLP118(E
- Part No.:
- TLP118(E
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- Logic Output Optoisolators
- Package:
- 6-SOIC (0.179", 4.55mm Width), 5 Leads
- Datasheet:
-
TLP118(E.pdf
- Description:
- X36 PB-F PHOTOCOUPLER SMD BULK J
- Quantity:
- Payment:

- Shipping:

Inventory:3,506
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TLP118(E) from Toshiba Electronic Devices & Storage Corporation is a high-speed, high-CMTI photocoupler with integrated IRED and photo-IC output stage, designed for isolated digital signal transmission in industrial control interfaces. It features open-collector logic inversion, ±15 kV/μs common-mode transient immunity, 60 ns max propagation delay, and guaranteed operation from −40°C to 125°C - enabling reliable use in plasma display panel (PDP) drive circuits and factory automation I/O modules.
For engineers reviewing the TLP118(E) datasheet, TLP118(E) pinout, TLP118(E) application, or TLP118(E) equivalent, key selection criteria include its SO6 package footprint, 4.5–5.5 V supply range, 5.0 mA max input threshold current, and UL/cUL/VDE safety certifications - all critical for noise-immune, high-temperature isolation in measurement instrumentation and motor control feedback paths.
Technical Context
The TLP118(E) implements an optically coupled inverter architecture: infrared LED input drives a high-gain, shielded photodetector IC whose output stage is an open-collector NPN transistor. Its internal Faraday shield ensures robustness against fast transients across the isolation barrier.
This device operates as a two-terminal isolation component (pins 1+3 shorted; pins 4+5+6 shorted per isolation rating), delivering logic-level compatibility with 5 V microcontrollers while maintaining 3750 Vrms isolation voltage and 5.0 mm creepage/clearance - meeting EN 60747-5-5 and UL 1577 requirements for reinforced insulation in industrial systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Voltage | 3750 Vrms min - supports reinforced insulation per UL 1577 and EN 62368-1 in mains-connected equipment. |
| Common-Mode Transient Immunity | ±15 kV/μs min - prevents false triggering in noisy motor drive or PDP scan circuits with rapid ground shifts. |
| Propagation Delay | 60 ns max (tpHL/tpLH) - enables ≥10 MHz digital signal isolation for real-time control loop feedback. |
| Supply Voltage Range | 4.5–5.5 V - matches standard 5 V logic rails without level-shifting circuitry. |
| Input Threshold Current | 5.0 mA max (IFH) - allows direct drive from MCU GPIOs or low-power logic gates without external amplification. |
| Operating Temperature | −40°C to 125°C - supports deployment in under-hood automotive ECUs, industrial PLCs, and PDP sustain driver stages. |
| Package | SO6 - surface-mount footprint compatible with automated assembly and provides 5.0 mm creepage/clearance for IPC-2221 Class B spacing. |
Pinout & Package
Package: SO6 (Mini-flat, 6-pin surface-mount). Pin 1: Anode; Pin 3: Cathode; Pins 4/5/6: GND/VO/VCC - internally grouped as output-side terminals per isolation rating.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Anode | LED anode connection; requires series resistor for current limiting from 3.3 V or 5 V logic sources. |
| 3 | Cathode | LED cathode; referenced to input-side ground - forms isolated input path with Pin 1. |
| 4 | GND | Output-side ground reference; tied internally to Pins 5 and 6 for isolation compliance. |
| 5 | VO | Open-collector output node; sinks up to 25 mA when active; requires external pull-up to VCC. |
| 6 | VCC | Output-side supply; powers photodetector IC; bypass capacitor (0.1 μF) mandatory between Pins 6 and 4. |
Key Features
| Feature | Design Value |
|---|---|
| Inverter logic output | Active-low open-collector interface simplifies connection to 5 V TTL/CMOS inputs and enables wired-OR bus configurations. |
| Faraday-shielded detector | Guarantees ±15 kV/μs CMTI - essential for stable operation in variable-frequency drives and high-dv/dt PDP electrode switching. |
| High-temperature operation | Rated from −40°C to 125°C ambient - eliminates derating concerns in enclosed industrial enclosures or near power semiconductors. |
| UL/cUL/VDE certified | Meets UL 1577, CSA Component Acceptance, and EN 60747-5-5 - reduces certification effort for end-equipment safety approvals. |
| Low propagation skew | ≤40 ns max propagation delay skew - ensures timing consistency across multiple channels in synchronized I/O modules. |
Applications
| Plasma Display Panel (PDP) Sustain Driver | Factory Automation I/O Module |
|---|---|
|
Use Scenario: Isolating high-voltage sustain pulse timing signals from low-voltage controller logic in AC-PDP panels. IC Role / Device Role / Timing Role: Level-shifting and noise-immune transmission of 200 kHz–500 kHz gate enable signals to sustain driver ICs operating at ±200 V. Use Value: ±15 kV/μs CMTI prevents misfiring during simultaneous electrode switching, ensuring uniform plasma cell illumination and eliminating visual artifacts. |
Use Scenario: Providing isolated digital input conditioning for 24 V DC sensor signals in programmable logic controllers (PLCs). IC Role / Device Role / Timing Role: Converting field-side 24 V on/off states into clean 5 V logic levels for microcontroller GPIOs with galvanic separation. Use Value: 125°C operation allows mounting directly on I/O carrier boards near power relays, reducing wiring complexity and board space vs. discrete opto + buffer solutions. |
| Industrial Measuring Instrument Interface | Motor Control Feedback Isolation |
|
Use Scenario: Isolating serial communication lines (e.g., RS-485 enable/disable control) in portable multimeters and power analyzers. IC Role / Device Role / Timing Role: Enabling/disabling transceiver drivers while blocking ground loops and ESD-induced latch-up in battery-powered test gear. Use Value: 3750 Vrms isolation and 5.0 mm creepage meet IEC 61010-1 CAT II 300 V requirements for handheld instrument safety certification. |
Use Scenario: Transmitting PWM fault signals from gate driver ICs to main controller in servo inverters. IC Role / Device Role / Timing Role: Fast, reliable transmission of overcurrent/overtemperature shutdown alerts (<100 ns latency budget) across isolation barrier. Use Value: 60 ns max propagation delay ensures sub-microsecond fault response - critical for preventing IGBT shoot-through and thermal runaway. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed photocoupler applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ACPL-K30T | SO5 package; 50 ns max tpHL/tpLH; 3750 Vrms isolation; no internal Faraday shield (CMTI = ±10 kV/μs). | Suitable for lower-noise environments like lab equipment; not recommended for PDP or VFD applications with >10 kV/μs transients. | Select when cost sensitivity outweighs extreme CMTI requirements and SO5 footprint is preferred. |
| PS9031 | SO6 package; 75 ns max tpHL/tpLH; ±25 kV/μs CMTI; higher IFH (8 mA max); requires external VCC decoupling only. | Better suited for ultra-high-noise motor control; higher input drive demand may require buffer in MCU-limited designs. | Choose for next-generation inverters where CMTI margin >20 kV/μs is mandated by system-level EMC testing. |
Compared with ACPL-K30T and PS9031, the TLP118(E) delivers optimal balance of speed (60 ns), CMTI (±15 kV/μs), and 5 V compatibility - making it the preferred choice for cost-constrained industrial PDP and PLC I/O designs requiring proven reliability at 125°C.
Availability
TLP118(E) is available at Aetrix Electronics and suitable for plasma display panel (PDP) sustain drivers, factory automation I/O modules, and industrial measuring instrument interfaces requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for TLP118(E) includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation designs and manufactures high-reliability semiconductor components for industrial, automotive, and consumer applications, with core expertise in power devices, logic ICs, and optoelectronics.
The TLP118(E) belongs to Toshiba's photocopler family engineered specifically for high-noise, high-temperature industrial isolation - emphasizing CMTI performance, safety certification, and extended temperature operation over general-purpose signal transfer.
FAQ
What is the maximum ambient temperature rating for the TLP118(E)?
The TLP118(E) is rated for continuous operation from −40°C to 125°C ambient temperature. This specification is validated across all electrical parameters including propagation delay, output saturation voltage, and common-mode transient immunity - enabling direct placement on heat-generating PCB sections in industrial motor drives and PDP sustain boards without thermal derating.
Does the TLP118(E) require an external bypass capacitor?
Yes, the TLP118(E) requires a 0.1 μF ceramic capacitor placed between Pin 6 (VCC) and Pin 4 (GND), with total lead length ≤1 cm. This bypass stabilizes the internal high-gain amplifier; omission causes increased propagation delay variation and potential false triggering under high dv/dt conditions - a requirement explicitly stated in the Toshiba datasheet Section 4.
What safety certifications does the TLP118(E) hold?
The TLP118(E) holds UL recognition (UL 1577, File No. E67349), cUL recognition (CSA Component Acceptance Service No. 5A, File No. E67349), and VDE approval (EN 60747-5-5 and EN 62368-1). These certifications apply to the base TLP118(E) variant; VDE-approved units require the V4 option suffix per Toshiba documentation.
Can the TLP118(E) be used with 3.3 V logic inputs?
Yes, the TLP118(E) can interface with 3.3 V logic inputs using a series current-limiting resistor. With IFH ≤5.0 mA max and VF ≈1.61 V typical at 10 mA, a 330 Ω resistor delivers ~5.8 mA at 3.3 V - well within absolute maximum ratings and sufficient to guarantee logic-low output. The datasheet confirms operation down to IF = 1.0 mA for reliable switching.
What is the isolation structure configuration of the TLP118(E)?
The TLP118(E) is configured as a two-terminal isolation device: Pins 1 and 3 (input side) are electrically shorted internally, and Pins 4, 5, and 6 (output side) are shorted - satisfying the 3750 Vrms isolation rating per UL 1577. This construction defines the minimum creepage and clearance distances (5.0 mm each) and must be respected in PCB layout to maintain certification integrity.
TLP118(E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Series:
- -
- Package/Case:
- 6-SOIC (0.179", 4.55mm Width), 5 Leads
- Packaging:
- Tube
- Product Status:
- Last Time Buy
- Number of Channels:
- 1
- Inputs - Side 1/Side 2:
- 1/0
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 15kV/µs
- Input Type:
- DC
- Output Type:
- Open Collector
- Current - Output / Channel:
- 25 mA
- Data Rate:
- -
- Propagation Delay tpLH / tpHL (Max):
- 60ns, 60ns
- Rise / Fall Time (Typ):
- 30ns, 30ns
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- 25mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-SO, 5 Lead
TLP118(E FAQ
1.How can I place an order for TLP118(E through Aetrix?
Please submit a Request for Quotation (RFQ) for TLP118(E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TLP118(E reliable?
The price and inventory of TLP118(E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TLP118(E is usually 5 days.
3.What payment methods are accepted for TLP118(E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TLP118(E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TLP118(E?
TLP118(E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TLP118(E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TLP118(E?
For technical support, including TLP118(E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TLP118(E requirements.
6.How does Aetrix verify that TLP118(E is sourced from the original manufacturer or authorized distributors?
All TLP118(E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TLP118(E meets industry standards.
7.What is the process for return or replacement of TLP118(E?
All TLP118(E units undergo pre-shipment inspection (PSI). If there is an issue with TLP118(E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TLP118(E part is unused and in its original packaging.
Return procedure for TLP118(E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TLP118(E Tags

-
6N137
Lite-On Inc.
-
6N137S
Lite-On Inc.
-
6N137S-TA1
Lite-On Inc.
-
TLP2362(TPR,E
Toshiba Semiconductor and Storage
-
H11L1M
onsemi
-
TLP2355(TPL,E
Toshiba Semiconductor and Storage
-
TLP2361(TPL,E
Toshiba Semiconductor and Storage
-
TLP2358(TPL,E)
Toshiba Semiconductor and Storage

-
H11L1SR2M
onsemi
-
TLP2361(V4-TPL,E
Toshiba Semiconductor and Storage
-
H11L1S(TA)
Everlight Electronics Co Ltd

-
H11L1SM
onsemi
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
