Toshiba Semiconductor and Storage TLP3409S(TP,E
- Part No.:
- TLP3409S(TP,E
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- Solid State Relays (SSR)
- Package:
- 4-SMD (0.079", 2.00mm)
- Datasheet:
-
TLP3409S(TP,E.pdf
- Description:
- SSR RELAY SPST-NO 650MA 0-100V
- Quantity:
- Payment:

- Shipping:

Inventory:15,748
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TLP3409S(TP,E from Toshiba Electronic Devices & Storage Corporation is a photorelay IC comprising an infrared LED optically coupled to a photo-MOSFET in a surface-mount S-VSON4T package. It delivers 0.65 A max ON-state current, 0.6 Ω max ON-resistance, and 100 V min OFF-state voltage-enabling high-speed switching in automated test equipment signal paths.
For engineers reviewing the TLP3409S(TP,E datasheet, TLP3409S(TP,E pinout, TLP3409S(TP,E application, or TLP3409S(TP,E equivalent, this device is selected for low-capacitance, galvanically isolated DC/low-frequency switching where compact size (1.45 mm × 2.0 mm), fast turn-on (0.3 ms typ.), and halogen-free packaging are critical.
Technical Context
The TLP3409S(TP,E implements optical isolation via GaAs LED-to-Si MOSFET coupling, with pins 1–2 internally shorted as the input anode/cathode pair and pins 3–4 shorted as the output drain terminals. Its two-terminal configuration simplifies PCB layout while maintaining 500 Vrms isolation.
It operates within –40°C to +110°C ambient, supports 5–80 V supply voltage, and requires ≤3.0 mA trigger LED current. Switching performance is characterized at IF = 5 mA and RL = 200 Ω, with tON/tOFF specified up to 2.0/0.3 ms max under those conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ON-state current | 0.65 A max - supports switching of logic-level and memory tester loads without external buffering |
| ON-state resistance | 0.6 Ω max - minimizes I²R loss and voltage drop in high-current probe card paths |
| OFF-state voltage | 100 V min - enables safe isolation across test channel voltage rails up to ±50 V |
| Trigger LED current | 3.0 mA max - allows direct drive from low-power FPGA I/O or microcontroller GPIO |
| Isolation voltage | 500 Vrms min - meets reinforced insulation requirements for Class I safety in ATE systems |
| Turn-on time | 0.3 ms typ. - enables sub-millisecond channel enable/disable sequencing in high-speed testers |
| Package | S-VSON4T (11-2E2) - 1.45 mm × 2.0 mm footprint with 1.4 mm height, optimized for dense probe card layouts |
Pinout & Package
S-VSON4T package (Toshiba designation 11-2E2), 4-pin surface-mount, 1.45 mm × 2.0 mm body, 1.4 mm max height, 0.01 g typical weight. Internally configured as two-terminal device: input side (pins 1–2) and output side (pins 3–4) are each shorted internally.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Anode | LED anode input; must be driven with current-limited source (≤30 mA abs max) |
| 2 | Cathode | LED cathode return; tied internally to Pin 1 for single-input connection |
| 3 | Drain | MOSFET drain terminal; tied internally to Pin 4 for dual-drain output configuration |
| 4 | Drain | Redundant drain terminal; provides parallel bond wire path to reduce RDS(on) and thermal resistance |
Key Features
| Feature | Design Value |
|---|---|
| Normally-open (1-Form-A) topology | Ensures fail-safe open-circuit behavior during LED deactivation or fault-critical for test channel protection |
| Halogen-free resin package | Complies with IPC-4101D/70 and JEDEC J-STD-020 moisture sensitivity level (MSL) 3 requirements |
| Low output capacitance | 1 pF max COFF - preserves signal integrity and bandwidth in >100 MHz logic tester channels |
| High OFF-state resistance | 10¹⁴ Ω min isolation resistance - prevents leakage-induced false triggering in high-impedance measurement nodes |
| ESD-sensitive design | HBM rating per JESD22-A114: not specified, but requires handling per Class 1A ESD controls (≤250 V) |
Applications
| Probe Cards | ATE Signal Routing |
|---|---|
Use Scenario: High-density wafer probe cards requiring isolated, low-Ron switching of DUT power and signal lines. IC Role / Device Role / Timing Role: Solid-state relay replacing mechanical relays for channel selection and power gating. Use Value: Enables 1.45 mm × 2.0 mm footprint per switch node, reducing probe card layer count and improving thermal dissipation vs. electromechanical alternatives. |
Use Scenario: Automatic Test Equipment backplane where multiple instrument channels share common bus architecture. IC Role / Device Role / Timing Role: Galvanically isolated analog/digital signal gate controlling stimulus/response path routing. Use Value: 500 Vrms isolation and 0.3 ms turn-on support synchronized channel enable across multi-site testers without ground-loop interference. |
| High-Speed Memory Testers | Measuring Instruments |
Use Scenario: DDR5/LPDDR5 memory testers performing simultaneous read/write line switching at >1 GHz data rates. IC Role / Device Role / Timing Role: Low-capacitance (<1 pF) ON/OFF switch isolating test head drivers from DUT termination networks. Use Value: Minimizes signal distortion and reflection due to parasitic capacitance-maintaining eye diagram integrity at 6.4 GT/s. |
Use Scenario: Precision multimeters and LCR meters requiring guarded switching of high-impedance sense inputs. IC Role / Device Role / Timing Role: Isolated multiplexer front-end protecting meter input stages from overvoltage transients. Use Value: 10¹⁴ Ω isolation resistance prevents measurement drift caused by leakage currents in <1 nA input circuits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar photorelay applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TLP3406S(TP,E | Lower ON-state current (0.4 A max), higher RON (1.0 Ω max), same S-VSON4T package | Better suited for lower-power probe card segments where thermal density is constrained | Select when system current demand is ≤400 mA and board space allows same footprint |
| PS8501-AX | SOIC-4 package (5.0 mm × 3.8 mm), 0.5 A max ION, 1.2 Ω max RON, 3750 Vrms isolation | Higher isolation voltage supports industrial mains-referenced test fixtures; larger footprint limits density | Choose for safety-critical ATE subsystems requiring reinforced isolation beyond 500 Vrms |
Compared with TLP3406S(TP,E and PS8501-AX, the TLP3409S(TP,E offers the highest current density (0.65 A in 2.9 mm²) and lowest RON among S-VSON4T photorelays, making it optimal for miniaturized, high-throughput test hardware where thermal and spatial constraints dominate.
Availability
TLP3409S(TP,E is available at Aetrix Electronics and suitable for probe cards, automatic test equipment, and high-speed memory testers requiring stable component supply, consistent MSL3 handling, and halogen-free compliance.
Supply support for TLP3409S(TP,E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation designs and manufactures discrete semiconductors, power devices, and optoelectronics with emphasis on reliability and industrial-grade performance.
The TLP3409S(TP,E belongs to Toshiba's photorelay product line, engineered specifically for high-density, high-speed semiconductor test infrastructure where miniaturization, low thermal resistance, and galvanic isolation are mandatory.
FAQ
What is the maximum continuous ON-state current rating for the TLP3409S(TP,E?
The TLP3409S(TP,E has a maximum continuous ON-state current rating of 0.65 A at Ta = 25°C. Derating applies above 25°C: –6.5 mA/°C. This rating is validated under recommended operating conditions with proper PCB copper area for thermal dissipation. The TLP3409S(TP,E must not exceed this limit to maintain reliability and avoid junction temperature violation.
Does the TLP3409S(TP,E support bidirectional current flow?
No, the TLP3409S(TP,E is a unidirectional photorelay with a normally-open (1-Form-A) configuration. Its internal MOSFET structure supports current flow only from drain to source in the forward direction, as defined by its absolute maximum ratings and electrical characteristics. Reverse conduction is not supported, and applying reverse voltage beyond specifications may damage the device. The TLP3409S(TP,E is not rated for AC or bidirectional switching.
What is the meaning of "(TP,E" in the TLP3409S(TP,E part number?
The suffix "(TP,E" denotes tape-and-reel packaging (TP) and RoHS-compliant, halogen-free resin (E). TP indicates the device is supplied in embossed carrier tape per EIA-481 standard, 2500 pcs per reel. The "E" confirms compliance with EU RoHS Directive 2011/65/EU and Toshiba's halogen-free specification (Br/Cl/Sb ≤0.09 wt%, total Br+Cl ≤0.15 wt%). The TLP3409S(TP,E is not lead-free in terminations unless separately specified.
Can the TLP3409S(TP,E be used in environments exceeding 110°C ambient temperature?
No, the TLP3409S(TP,E has a specified operating temperature range of –40°C to +110°C. Exceeding +110°C ambient violates the absolute maximum rating for Topr and risks irreversible degradation of the LED efficiency, MOSFET threshold stability, and encapsulant integrity. For higher-temperature applications, consider thermally derated operation with external heatsinking or alternative devices rated to 125°C junction, such as the TLP3410S(TP,E. The TLP3409S(TP,E must remain within its published thermal envelope.
How is isolation verified for the TLP3409S(TP,E during production testing?
Toshiba performs 100% production isolation voltage screening on the TLP3409S(TP,E at 500 Vrms AC for 60 seconds per JEDEC JESD22-B111. Each unit is tested with input-output dielectric withstand verification, and isolation resistance (≥10¹⁴ Ω) is sampled per lot. The TLP3409S(TP,E datasheet specifies these as minimum guaranteed parameters-not typical values-and they apply under standard humidity conditions (R.H. ≤60%). No additional third-party certification (e.g., UL, VDE) is included with the base TLP3409S(TP,E.
TLP3409S(TP,E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Series:
- TLP3409S
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Mounting Type:
- Surface Mount
- Circuit:
- SPST-NO (1 Form A)
- Output Type:
- AC, DC
- Voltage - Input:
- 1.27VDC
- Voltage - Load:
- 0 V ~ 100 V
- Load Current:
- 650 mA
- On-State Resistance (Max):
- 600 mOhms
- Termination Style:
- SMD (SMT) Tab
- Operating Temperature:
- -40°C ~ 110°C
- Supplier Device Package:
- 4-S-VSON
- Approval Agency:
- -
- Grade:
- -
- Qualification:
- -
TLP3409S(TP,E FAQ
1.How can I place an order for TLP3409S(TP,E through Aetrix?
Please submit a Request for Quotation (RFQ) for TLP3409S(TP,E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TLP3409S(TP,E reliable?
The price and inventory of TLP3409S(TP,E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TLP3409S(TP,E is usually 5 days.
3.What payment methods are accepted for TLP3409S(TP,E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TLP3409S(TP,E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TLP3409S(TP,E?
TLP3409S(TP,E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TLP3409S(TP,E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TLP3409S(TP,E?
For technical support, including TLP3409S(TP,E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TLP3409S(TP,E requirements.
6.How does Aetrix verify that TLP3409S(TP,E is sourced from the original manufacturer or authorized distributors?
All TLP3409S(TP,E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TLP3409S(TP,E meets industry standards.
7.What is the process for return or replacement of TLP3409S(TP,E?
All TLP3409S(TP,E units undergo pre-shipment inspection (PSI). If there is an issue with TLP3409S(TP,E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TLP3409S(TP,E part is unused and in its original packaging.
Return procedure for TLP3409S(TP,E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TLP3409S(TP,E Tags
.jpg)
-
G3VM-21UR11(TR05)
Omron Electronics Inc-EMC Div

-
G3VM-61VY3(TR05)
Omron Electronics Inc-EMC Div

-
CPC1017NTR
Littelfuse Inc.

-
CPC1017N
Littelfuse Inc.

-
CPC1006N
Littelfuse Inc.

-
VO1400AEFTR
Vishay Semiconductor Opto Division

-
CPC1006NTR
Littelfuse Inc.

-
TLP175A(TPL,E
Toshiba Semiconductor and Storage

-
CPC1002NTR
Littelfuse Inc.

-
AQY280S
Panasonic Electric Works

-
CPC1117NTR
Littelfuse Inc.

-
CPC1106NTR
Littelfuse Inc.
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

