Toshiba Semiconductor and Storage TLP3475(TP,F
- Part No.:
- TLP3475(TP,F
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- Solid State Relays (SSR)
- Package:
- 4-SMD (0.096", 2.45mm)
- Datasheet:
-
TLP3475(TP,F.pdf
- Description:
- SSR RELAY SPST-NO 300MA 0-50V
- Quantity:
- Payment:

- Shipping:

Inventory:23,311
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Product details
Overview
TLP3475(TP,F from Toshiba Electronic Devices & Storage Corporation is a photorelay IC comprising an infrared LED optically coupled to a photo MOSFET in a WSON4 package. It delivers 0.4 A max on-state current, 1.5 Ω max on-resistance, and 12 pF typ output capacitance for high-frequency signal routing in automated test equipment.
For engineers reviewing the TLP3475(TP,F datasheet, TLP3475(TP,F pinout, TLP3475(TP,F application, or TLP3475(TP,F equivalent, key selection criteria include insertion loss at 20 GHz, isolation voltage (300 Vrms), trigger LED current (≤3 mA), and low-profile WSON4 footprint compatibility with probe card layouts.
Technical Context
The TLP3475(TP,F implements optical isolation between input LED and output photo MOSFET, enabling galvanic separation while maintaining signal integrity up to 20 GHz. Its normally-open (1-Form-A) configuration supports single-pole switching with dual-drain outputs shorted internally.
It operates with 5–48 V supply voltage and requires ≤3 mA LED forward current to trigger conduction. The device sustains 60 V off-state output voltage and exhibits 0.1–0.25 ms turn-on time under 20 V/200 Ω load conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ON-state resistance | 1.5 Ω max - ensures minimal I²R heating and voltage drop at 0.4 A load current |
| Output capacitance | 12 pF typ / 20 pF max - enables <1% signal distortion for >1 GHz digital test waveforms |
| Insertion loss | 3 dB typ @ 20 GHz - preserves edge fidelity of rapidly rising test signals |
| Isolation voltage | 300 Vrms min - provides safety-rated barrier for mixed-signal ATE channel isolation |
| Trigger LED current | 3 mA max - allows direct drive from low-power logic or FPGA I/O without external amplification |
| OFF-state output voltage | 60 V min - supports biasing of high-voltage DUTs in memory and logic testers |
| Turn-on time | 0.1 ms typ - meets sub-microsecond switching requirements in high-speed pattern generators |
Pinout & Package
Package: WSON4 (1.45 mm × 2.0 mm, 0.8 mm height), halogen-free resin, 0.01 g typical weight. Pin assignment follows Toshiba's 11-2F1A land pattern.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (Anode) | LED anode | Positive input for infrared LED; connects to driver source or logic-high signal |
| 2 (Cathode) | LED cathode | LED return path; ties to ground or sink driver for optical activation |
| 3 & 4 (Drain) | Photo MOSFET drain terminals | Internally shorted output nodes; used as single-switch output with dual-pad layout for low-inductance routing |
Key Features
| Feature | Design Value |
|---|---|
| Low CR product | Combines low capacitance (12 pF) and low resistance (1.5 Ω) to minimize RC delay in RF paths |
| High-frequency signal integrity | 3 dB insertion loss at 20 GHz enables use in >10 Gbps serial test interfaces |
| Compact WSON4 footprint | 1.45 × 2.0 mm area supports dense probe card layouts without sacrificing thermal performance |
| Halogen-free construction | Meets IPC-4101D/102 for environmentally compliant manufacturing in test equipment assemblies |
| Low off-state current | 1 nA max at 50 V ensures negligible leakage during high-impedance measurement phases |
Applications
| High-Speed Memory Testers | High-Speed Logic IC Testers |
|---|---|
Use Scenario: Routing test vectors and sense lines between ATE controller and DDR5/LPDDR5 DUTs with minimal signal degradation. IC Role / Device Role / Timing Role: Signal-path switch isolating tester channels during parallel test execution. Use Value: 20 GHz insertion loss spec maintains rise/fall times <35 ps for accurate timing margin validation. | Use Scenario: Enabling/disabling stimulus paths to multi-core SoCs or FPGA-based logic analyzers during functional pattern testing. IC Role / Device Role / Timing Role: High-speed channel selector with sub-100 ns switching for synchronized vector delivery. Use Value: 0.1 ms turn-on time supports >10 MHz pattern rates without inter-symbol interference. |
| Automatic Test Equipment (ATE) | Probe Cards |
Use Scenario: Isolating power domains and signal paths across modular ATE backplanes to prevent crosstalk and ground bounce. IC Role / Device Role / Timing Role: Galvanically isolated relay for channel-to-channel signal routing and power sequencing control. Use Value: 300 Vrms isolation rating enables safe operation between ±24 V analog supplies and 3.3 V digital logic domains. | Use Scenario: Integrating into MEMS or vertical probe card substrates where space and parasitic capacitance are critical constraints. IC Role / Device Role / Timing Role: Miniaturized, low-COSS switch for per-pin signal conditioning and calibration path selection. Use Value: 12 pF output capacitance minimizes loading on 50 Ω transmission lines, preserving impedance matching. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar photorelay applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TLP3477(TP,F | Higher 1.2 A max on-state current; same WSON4 package and 20 GHz insertion loss | Better suited for higher-current DUT power switching; not optimized for ultra-low capacitance | Select TLP3477(TP,F only when >0.4 A load capability is required and 20 pF max COFF remains acceptable |
| PS9031-Y-V-AX | SO-6 package; 1.5 A max ION; 35 pF max COFF; 10 MHz bandwidth limit | Larger footprint and lower frequency response; designed for industrial PLC I/O, not RF test | Choose PS9031-Y-V-AX only for cost-sensitive, non-RF applications where board space and speed are secondary |
Compared with TLP3475(TP,F, the TLP3477(TP,F offers higher current handling but identical RF performance, while the PS9031-Y-V-AX trades bandwidth and size for higher current and legacy packaging-making TLP3475(TP,F optimal for space-constrained, >10 Gbps ATE signal routing.
Availability
TLP3475(TP,F is available at Aetrix Electronics and suitable for high-speed memory testers, automatic test equipment, and probe card assemblies requiring stable component supply, RoHS-compliant packaging, and traceable sourcing.
Supply support for TLP3475(TP,F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation designs high-reliability semiconductor components for industrial, automotive, and test equipment markets, with emphasis on optical isolation and power efficiency.
The TLP3475(TP,F belongs to Toshiba's photorelay product line engineered specifically for high-frequency signal routing in automated test systems, balancing low on-resistance, ultra-low capacitance, and compact WSON packaging.
FAQ
What is the maximum operating temperature for the TLP3475(TP,F?
The TLP3475(TP,F has a specified operating temperature range of –40 °C to +110 °C. Its junction temperature must not exceed +125 °C under continuous operation. Derating of ON-state current begins at +25 °C ambient, with –4 mA/°C reduction above that point to maintain reliability and thermal stability in high-density ATE modules.
Does the TLP3475(TP,F support DC and AC signal switching?
Yes, the TLP3475(TP,F supports both DC and AC signal switching up to 20 GHz due to its low 12 pF output capacitance and 3 dB insertion loss at that frequency. It is rated for 60 V off-state voltage and 0.4 A continuous on-state current, making it suitable for DC-coupled test paths and high-frequency AC signal routing in logic and memory testers.
What is the pin configuration and internal connection of pins 3 and 4 on the TLP3475(TP,F?
Pins 3 and 4 of the TLP3475(TP,F are both drain terminals of the internal photo MOSFET and are shorted together internally per Toshiba's datasheet Note 1. This dual-pad configuration reduces inductance and improves current sharing, allowing use as a single-output switch with enhanced thermal dissipation in WSON4 layout.
Is the TLP3475(TP,F halogen-free and RoHS compliant?
Yes, the TLP3475(TP,F uses halogen-free resin packaging per Toshiba's specification, with bromine, chlorine, and antimony each below 0.09 wt% and total halogens <0.15 wt%. RoHS compliance (Directive 2011/65/EU) is confirmed by the "E" suffix in the ordering code TLP3475(TP,F, indicating full environmental conformance for EU market deployment.
How does the TLP3475(TP,F achieve low insertion loss at 20 GHz?
The TLP3475(TP,F achieves 3 dB typ insertion loss at 20 GHz through co-optimized die design and WSON4 package parasitics: ultra-low 12 pF output capacitance, minimized bond wire inductance, and symmetric dual-drain layout reduce impedance discontinuities. These features collectively preserve signal integrity for fast-rising edges in high-speed ATE applications without external matching networks.
TLP3475(TP,F Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Series:
- TLP3475
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Mounting Type:
- Surface Mount
- Circuit:
- SPST-NO (1 Form A)
- Output Type:
- AC, DC
- Voltage - Input:
- 1.27VDC
- Voltage - Load:
- 0 V ~ 50 V
- Load Current:
- 300 mA
- On-State Resistance (Max):
- 1.5 Ohms
- Termination Style:
- SMD (SMT) Tab
- Operating Temperature:
- -40°C ~ 110°C
- Supplier Device Package:
- 4-VSON (1.45x2.45)
- Approval Agency:
- -
- Grade:
- -
- Qualification:
- -
TLP3475(TP,F FAQ
1.How can I place an order for TLP3475(TP,F through Aetrix?
Please submit a Request for Quotation (RFQ) for TLP3475(TP,F on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TLP3475(TP,F reliable?
The price and inventory of TLP3475(TP,F are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TLP3475(TP,F is usually 5 days.
3.What payment methods are accepted for TLP3475(TP,F?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TLP3475(TP,F transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TLP3475(TP,F?
TLP3475(TP,F orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TLP3475(TP,F order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TLP3475(TP,F?
For technical support, including TLP3475(TP,F datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TLP3475(TP,F requirements.
6.How does Aetrix verify that TLP3475(TP,F is sourced from the original manufacturer or authorized distributors?
All TLP3475(TP,F products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TLP3475(TP,F meets industry standards.
7.What is the process for return or replacement of TLP3475(TP,F?
All TLP3475(TP,F units undergo pre-shipment inspection (PSI). If there is an issue with TLP3475(TP,F, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TLP3475(TP,F part is unused and in its original packaging.
Return procedure for TLP3475(TP,F:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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