Toshiba Semiconductor and Storage TLP352(D4,F)
- Part No.:
- TLP352(D4,F)
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- Isolators - Gate Drivers
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
TLP352(D4,F).pdf
- Description:
- OPTOISO 3.75KV 1CH GATE DVR 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,018
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Product details
Overview
TLP352(D4,F) from Toshiba Electronic Devices & Storage Corporation is a high-speed, high-isolation photocoupler with GaAlAs infrared LED and integrated photo IC in DIP8 through-hole package. It delivers ±2.5 A peak output current, 200 ns max propagation delay, and ±20 kV/µs common-mode transient immunity for robust gate driving of IGBTs and power MOSFETs in industrial inverters and induction cooktops.
For engineers reviewing the TLP352(D4,F) datasheet, TLP352(D4,F) pinout, TLP352(D4,F) application, or TLP352(D4,F) equivalent, this device is selected for high-reliability isolated gate drive where 3750 Vrms isolation, -40 to 125 °C operation, and totem-pole output sourcing/sinking capability are required in safety-critical power conversion systems.
Technical Context
The TLP352(D4,F) integrates an optically coupled GaAlAs LED and high-gain photodetector IC with internal Faraday shield, enabling guaranteed ±20 kV/µs CMTI at up to 125 °C ambient. Its totem-pole output stage supports bidirectional current flow (±2.5 A peak), eliminating external pull-up/pull-down components in gate drive circuits.
It operates from 15–30 V supply with UVLO protection (11.0–13.5 V threshold), requires ≤5 mA input threshold current, and mandates a 0.1 µF bypass capacitor between pins 8 (VCC) and 5 (GND) for stable high-speed switching - critical for clean IGBT turn-on/turn-off in motor drives and home appliance inverters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Voltage | 3750 Vrms min - meets reinforced insulation requirements for industrial mains-connected equipment per UL1577 and EN60747-5-5 (D4 option). |
| Output Peak Current | ±2.5 A max - directly drives IGBT/MOSFET gates without external buffer stages in high-power switching applications. |
| Propagation Delay | 200 ns max - enables precise timing control in 50 kHz PWM systems like induction heating and servo motor inverters. |
| CMTI | ±20 kV/µs min - suppresses false triggering during fast dv/dt transients in high-voltage power stages. |
| Operating Temperature | -40 to 125 °C - supports deployment in under-hood automotive auxiliary inverters and sealed industrial enclosures. |
| Supply Voltage Range | 15–30 V - compatible with standard 24 V control rails and provides margin for ripple-induced droop in noisy environments. |
| Threshold Input Current | 5 mA max - ensures reliable turn-on with standard microcontroller GPIO or logic-level drivers without additional current amplification. |
Pinout & Package
Package: DIP8 through-hole (TOSHIBA 11-10C402S), 10.16 mm pitch, creepage/clearance ≥8.0 mm, isolation thickness ≥0.4 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | No Connect | Internally unconnected; must remain floating or tied to GND per layout best practice to minimize coupling. |
| 2 | Anode | LED anode input; requires series resistor to limit IF to 5–10 mA for reliable switching and longevity. |
| 3 | Cathode | LED cathode return; connects to MCU/GPIO low-side driver or ground reference. |
| 4 | No Connect | Internally unconnected; leave unpopulated or tie to GND for symmetry and EMI reduction. |
| 5 | GND | Photodetector IC ground reference; must be low-impedance connection to system power ground plane. |
| 6 | VO (Output) | Totem-pole output node; sources/sinks current to drive gate of N-channel IGBT/MOSFET directly. |
| 7 | No Connect | Internally unconnected; no electrical function; avoid routing signals nearby to prevent crosstalk. |
| 8 | VCC | Photodetector supply; requires 0.1 µF ceramic bypass capacitor placed ≤1 cm from pin to GND (pin 5) for stability. |
Key Features
| Feature | Design Value |
|---|---|
| Buffer logic output | Totem-pole configuration enables active high/low drive without external pull resistors - reduces BOM count and PCB area in gate driver designs. |
| UVLO protection | 11.0–13.5 V hysteresis prevents erratic output during brown-out conditions, ensuring safe gate voltage collapse before supply stabilizes. |
| D4 safety certification | EN60747-5-5 qualified variant (TLP352(D4,F)) - certified for reinforced insulation in medical and industrial safety-critical systems. |
| High CMTI | ±20 kV/µs minimum - maintains signal integrity across isolation barrier during rapid bus voltage transients in 600–1200 V DC-link applications. |
| Wide temperature range | -40 to 125 °C operation - validated for use in sealed motor drives, EV charging modules, and induction cooktop control boards. |
Applications
| Industrial Inverters | MOSFET Gate Drivers |
|---|---|
Use Scenario: Isolated gate drive in 3-phase VFDs for HVAC compressors and pump motors operating at 400–690 V AC mains. IC Role / Device Role / Timing Role: Primary isolation interface between MCU PWM outputs and high-side/lower-side IGBT half-bridge gates. Use Value: ±2.5 A peak output current and 200 ns propagation delay enable <1 µs dead-time control, minimizing shoot-through risk in 16 kHz PWM systems. |
Use Scenario: Direct gate driving of 650 V SiC MOSFETs in high-efficiency server PSU PFC and LLC stages. IC Role / Device Role / Timing Role: Level-shifting and noise-immune signal transmission from low-voltage controller to high-voltage power stage. Use Value: ±20 kV/µs CMTI prevents false turn-on during 50 V/ns dv/dt events on 400 V DC bus, improving system reliability over standard optocouplers. |
| IGBT Gate Drivers | Induction Cooktop and Home Appliances |
Use Scenario: Driving 1200 V IGBTs in induction heating resonant inverters for commercial kitchen equipment. IC Role / Device Role / Timing Role: High-current isolated gate driver with UVLO monitoring for fault-safe shutdown during overvoltage or undervoltage events. Use Value: 3750 Vrms isolation and EN60747-5-5 (D4) qualification meet IEC61800-5-1 requirements for functional safety in Class I appliances. |
Use Scenario: Compact, thermally robust gate drive in sealed induction cooktop control modules exposed to >85 °C ambient. IC Role / Device Role / Timing Role: Signal isolator interfacing microcontroller PWM to half-bridge gate drivers in space-constrained PCB layouts. Use Value: -40 to 125 °C rating and 0.1 µF bypass capacitor requirement ensure stable operation without thermal derating in enclosed metal housings. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed photocoupler gate drive applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ACPL-332J | SO-6 package (surface-mount), 2.5 A peak output, 250 ns max propagation delay, 5000 Vrms isolation. | Requires rework for SMT assembly; higher isolation but slower switching than TLP352(D4,F). | Select when board space is constrained and SMT process is available; verify layout clearance for 5000 Vrms creepage. |
| HCPL-316J | DIP8 package, 2.5 A peak output, 500 ns max propagation delay, ±15 kV/µs CMTI, 3750 Vrms isolation. | Slower switching and lower CMTI limit suitability in high-frequency (>20 kHz) or high-dv/dt (>10 kV/µs) applications. | Choose for legacy compatibility or cost-sensitive designs where 500 ns delay is acceptable; not recommended for new 50 kHz induction cooktop designs. |
Compared with ACPL-332J and HCPL-316J, the TLP352(D4,F) offers superior speed (200 ns vs. 250/500 ns) and CMTI (±20 kV/µs vs. ±15 kV/µs), making it optimal for high-frequency, high-noise industrial inverters requiring tight timing control and reinforced safety certification.
Availability
TLP352(D4,F) is available at Aetrix Electronics and suitable for industrial inverters, IGBT gate drivers, and induction cooktop control systems requiring stable component supply with long-term lifecycle assurance.
Supply support for TLP352(D4,F) includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation is a Japanese semiconductor manufacturer specializing in power devices, optoelectronics, and storage solutions with global manufacturing and quality certifications.
The TLP352 series belongs to Toshiba's high-reliability photocoupler product line, engineered specifically for isolated gate driving in industrial motor controls, renewable energy inverters, and home appliance power systems demanding safety, speed, and thermal resilience.
FAQ
What is the safety certification status of TLP352(D4,F)?
The TLP352(D4,F) is qualified to EN60747-5-5 under Option D4, meeting reinforced insulation requirements for industrial and household appliances. It carries UL1577 (File No. E67349) and cUL CSA Component Acceptance (File No. E67349) approvals. The "(D4,F)" suffix explicitly denotes compliance with this enhanced safety standard, unlike base TLP352 variants.
Does TLP352(D4,F) require an external bypass capacitor?
Yes, TLP352(D4,F) requires a 0.1 µF ceramic capacitor connected between pin 8 (VCC) and pin 5 (GND), placed within 1 cm of both pins. This capacitor stabilizes the internal photodetector IC's high-gain amplifier and prevents improper switching or oscillation - omission causes unreliable gate drive behavior per Toshiba's datasheet Note in Section 6 and 9.
What is the maximum allowable dV/dt on the input side of TLP352(D4,F)?
TLP352(D4,F) does not specify a maximum input-side dV/dt rating. Its input is a GaAlAs LED (pins 2–3), which behaves as a diode - reverse voltage is limited to 5 V max (per Absolute Maximum Ratings). Transient suppression must be implemented externally if the input circuit is exposed to high dv/dt; the device's ±20 kV/µs CMTI applies only to the isolation barrier (input-to-output), not input terminal stress.
Can TLP352(D4,F) drive both high-side and low-side IGBT gates directly?
Yes, TLP352(D4,F)'s totem-pole output (pin 6) can both source and sink up to ±2.5 A peak current, enabling direct drive of low-side IGBT gates (sink mode) and high-side gates when paired with a bootstrap or isolated supply. Its 15–30 V VCC range supports standard gate drive voltages, and UVLO ensures safe disable below 11.0 V - critical for preventing partial turn-on.
What is the difference between TLP352(D4,F) and TLP352F?
TLP352(D4,F) is the EN60747-5-5 Option D4 qualified version of TLP352F, with identical DIP8 package (11-10C402S), pinout, and electrical specs. The "(D4)" denotes formal certification to the higher insulation standard required for safety-critical applications; "(F)" indicates RoHS-compliant construction. Standard TLP352F lacks D4 qualification and cannot be used where EN60747-5-5 compliance is mandated.
TLP352(D4,F) Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Technology:
- Optical Coupling
- Number of Channels:
- 1
- Voltage - Isolation:
- 3750Vrms
- Common Mode Transient Immunity (Min):
- 20kV/µs
- Propagation Delay tpLH / tpHL (Max):
- 200ns, 200ns
- Pulse Width Distortion (Max):
- 50ns
- Rise / Fall Time (Typ):
- 15ns, 8ns
- Current - Output High, Low:
- 2A, 2A
- Current - Peak Output:
- 2.5A
- Voltage - Forward (Vf) (Typ):
- 1.55V
- Current - DC Forward (If) (Max):
- 20 mA
- Voltage - Output Supply:
- 15V ~ 30V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-DIP
- Approval Agency:
- CSA, cUL, UL, VDE
TLP352(D4,F) FAQ
1.How can I place an order for TLP352(D4,F) through Aetrix?
Please submit a Request for Quotation (RFQ) for TLP352(D4,F) on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TLP352(D4,F) reliable?
The price and inventory of TLP352(D4,F) are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TLP352(D4,F) is usually 5 days.
3.What payment methods are accepted for TLP352(D4,F)?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TLP352(D4,F) transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TLP352(D4,F)?
TLP352(D4,F) orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TLP352(D4,F) order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TLP352(D4,F)?
For technical support, including TLP352(D4,F) datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TLP352(D4,F) requirements.
6.How does Aetrix verify that TLP352(D4,F) is sourced from the original manufacturer or authorized distributors?
All TLP352(D4,F) products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TLP352(D4,F) meets industry standards.
7.What is the process for return or replacement of TLP352(D4,F)?
All TLP352(D4,F) units undergo pre-shipment inspection (PSI). If there is an issue with TLP352(D4,F), returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TLP352(D4,F) part is unused and in its original packaging.
Return procedure for TLP352(D4,F):
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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