Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Isolators > Isolators - Gate Drivers

Toshiba Semiconductor and Storage TLP5754(LF4,E

Name: TLP5754(LF4,E
Brand: Toshiba Semiconductor and Storage
SKU: TLP5754(LF4,E
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: TLP5754(LF4,E

Manufacturer:: Toshiba Semiconductor and Storage

Category:: Isolators - Gate Drivers

Package:: 6-SOIC (0.295", 7.50mm Width)

Datasheet:: TLP5754(LF4,E.pdf

Description:: OPTOISO 5KV 1CH GATE DVR 6SO

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:125

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

TLP5754(LF4,E) from Toshiba Electronic Devices & Storage Corporation is a high-speed, reinforced-insulation photocoupler with integrated photo-IC output stage, designed for gate driving of power MOSFETs and IGBTs in high-noise industrial inverters and home appliance motor controls. It delivers ±4.0 A peak output current, 150 ns max propagation delay, ±35 kV/µs common-mode transient immunity, and operates across –40°C to +110°C with 15–30 V supply voltage.

For engineers reviewing the TLP5754(LF4,E) datasheet, TLP5754(LF4,E) pinout, TLP5754(LF4,E) application, or TLP5754(LF4,E) equivalent, this page provides verified technical context, safety-certified isolation specs, rail-to-rail totem-pole output behavior, and real-world design guidance for high-reliability gate drive circuits requiring UL, cUL, VDE, and CQC safety approvals.

Technical Context

The TLP5754(LF4,E) integrates an infrared LED input stage with a monolithic high-gain photodetector and totem-pole buffer output, enabling direct connection to power device gates without external amplification. Its internal Faraday shield ensures ±35 kV/µs common-mode transient immunity - critical for fast-switching inverter applications where dV/dt noise exceeds 10 kV/µs.

This device implements a logic-level truth table (H/L input → H/L output), supports rail-to-rail output swing (VOH ≥ 12.1 V, VOL ≤ 0.2 V at rated load), and requires a mandatory 1 µF ceramic bypass capacitor between VCC (Pin 6) and GND (Pin 4) placed within 1 cm to stabilize high-gain operation and prevent oscillation.

Key Specifications

Parameter	Value and Actual Design Meaning
Isolation Voltage	5000 Vrms min - meets reinforced insulation requirements per UL 1577, EN IEC 60747-5-5, and GB4943.1 for mains-connected equipment.
Output Peak Current	±4.0 A max - drives high-input-capacitance IGBTs/MOSFETs directly without external buffers, reducing BOM count and layout area.
Propagation Delay	tpHL/tpLH ≤ 150 ns - enables >50 kHz switching frequencies in motor control and induction cooktop inverters with tight timing margins.
Common-Mode Immunity	±35 kV/µs min - suppresses false triggering during rapid bus voltage transients in 600 V+ DC-link systems.
Supply Voltage Range	15–30 V - compatible with standard industrial 24 V rails and supports undervoltage lockout (UVLO) at 12.1 V (rising) / 11.1 V (falling).
Operating Temperature	–40°C to +110°C - qualified for under-hood automotive-adjacent environments and sealed inverter enclosures without derating.
Threshold Input Current	≤4 mA max - ensures reliable turn-on with low-power MCU GPIOs or isolated logic drivers, minimizing driver-stage power loss.

Pinout & Package

Package: 6-pin SO6L (Toshiba package code 11-4N101A), surface-mount, lead-forming option LF4 (wide forming), 2.3 mm max height, 8.0 mm min creepage/clearance, 0.4 mm min internal isolation thickness.

Pin/Terminal	Circuit Role	Design Meaning
1: Anode	LED anode input	Connects to current-limited logic or MCU output; requires ≥6 mA IF(ON) for guaranteed turn-on.
2: N.C.	No connect	Internally unconnected; must remain floating - no routing or soldering allowed.
3: Cathode	LED cathode return	Completes LED forward path; ties to ground or logic low reference on input side.
4: GND	Output-stage ground	Reference for VO output and UVLO monitoring; requires low-inductance 1 µF bypass to Pin 6.
5: VO	Buffered output terminal	Rail-to-rail totem-pole driver output; connects directly to MOSFET/IGBT gate; sinks or sources up to ±4 A.
6: VCC	Output-stage supply	Power input for photodetector and buffer; must be decoupled to Pin 4 with 1 µF ceramic capacitor within 1 cm.

Key Features

Feature	Design Value
Reinforced insulation	5000 Vrms isolation with VDE EN IEC 60747-5-5, UL 1577, and CQC certification - eliminates need for external isolation barriers in Class I/II appliances.
Rail-to-rail totem-pole output	VOH ≥ 12.1 V and VOL ≤ 0.2 V at full load - ensures strong gate overdrive and clean zero-volt turn-off for robust MOSFET/IGBT switching.
Integrated Faraday shield	Guarantees ±35 kV/µs CMTI - prevents false triggering in high-dV/dt inverter half-bridges without added shielding or layout constraints.
UVLO protection	12.1 V (rising) / 11.1 V (falling) threshold - disables output during brown-out conditions to avoid partial gate drive and device destruction.
Compact SO6L footprint	50% smaller than legacy 8-pin DIP - reduces PCB area by >30% while maintaining creepage/clearance compliance for safety-critical designs.

Applications

Induction Cooktop Control	Air Conditioner Inverter
Use Scenario: Driving high-side and low-side IGBTs in resonant half-bridge topology operating at 20–50 kHz with 600 V DC-link. IC Role / Device Role / Timing Role: Isolated gate driver providing level-shifted, noise-immune PWM signals with <150 ns propagation matching for precise dead-time control. Use Value: ±35 kV/µs CMTI prevents shoot-through during fast bus transients; rail-to-rail output ensures full gate overdrive even at elevated temperature.	Use Scenario: Controlling compressor PMSM motor via 3-phase inverter in variable-refrigerant-flow (VRF) systems with ambient temperatures up to 60°C. IC Role / Device Role / Timing Role: High-current gate driver interfacing MCU PWM outputs to IGBT modules, delivering ±4 A peak to charge/discharge 10 nF+ gate capacitances. Use Value: –40°C to +110°C rating enables operation inside sealed outdoor units; 5000 Vrms isolation satisfies IEC 60335-1 for household appliance safety.
Industrial Motor Drive	MOSFET-Based UPS Output Stage
Use Scenario: Gate driving 1200 V IGBTs in 3-phase 10 kW servo drives exposed to EMI from adjacent contactors and braking resistors. IC Role / Device Role / Timing Role: Reinforced-isolation interface between controller FPGA and power stage, rejecting common-mode noise induced by fast-switching and grounding loops. Use Value: Internal Faraday shield eliminates need for external CM chokes; SO6L package allows dense gate-driver layout without compromising creepage distance.	Use Scenario: Driving paralleled 650 V SiC MOSFETs in online double-conversion UPS output inverters requiring <200 ns total propagation skew across six channels. IC Role / Device Role / Timing Role: High-speed, matched-propagation gate driver ensuring synchronous switching across phase-legs to minimize circulating currents and THD. Use Value: tpLH/tpHL ≤ 150 ns with <80 ns pulse width distortion enables sub-microsecond timing alignment; 15–30 V VCC range accommodates wide-input auxiliary supplies.

Induction Cooktop Control

Air Conditioner Inverter

Use Scenario: Driving high-side and low-side IGBTs in resonant half-bridge topology operating at 20–50 kHz with 600 V DC-link.

IC Role / Device Role / Timing Role: Isolated gate driver providing level-shifted, noise-immune PWM signals with <150 ns propagation matching for precise dead-time control.

Use Value: ±35 kV/µs CMTI prevents shoot-through during fast bus transients; rail-to-rail output ensures full gate overdrive even at elevated temperature.

Use Scenario: Controlling compressor PMSM motor via 3-phase inverter in variable-refrigerant-flow (VRF) systems with ambient temperatures up to 60°C.

IC Role / Device Role / Timing Role: High-current gate driver interfacing MCU PWM outputs to IGBT modules, delivering ±4 A peak to charge/discharge 10 nF+ gate capacitances.

Use Value: –40°C to +110°C rating enables operation inside sealed outdoor units; 5000 Vrms isolation satisfies IEC 60335-1 for household appliance safety.

Industrial Motor Drive

MOSFET-Based UPS Output Stage

Use Scenario: Gate driving 1200 V IGBTs in 3-phase 10 kW servo drives exposed to EMI from adjacent contactors and braking resistors.

IC Role / Device Role / Timing Role: Reinforced-isolation interface between controller FPGA and power stage, rejecting common-mode noise induced by fast-switching and grounding loops.

Use Value: Internal Faraday shield eliminates need for external CM chokes; SO6L package allows dense gate-driver layout without compromising creepage distance.

Use Scenario: Driving paralleled 650 V SiC MOSFETs in online double-conversion UPS output inverters requiring <200 ns total propagation skew across six channels.

IC Role / Device Role / Timing Role: High-speed, matched-propagation gate driver ensuring synchronous switching across phase-legs to minimize circulating currents and THD.

Use Value: tpLH/tpHL ≤ 150 ns with <80 ns pulse width distortion enables sub-microsecond timing alignment; 15–30 V VCC range accommodates wide-input auxiliary supplies.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed gate driver photocoupler applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ACPL-332J-500E	SO-6 package, ±2.5 A peak output, 100 ns max propagation, 3750 Vrms isolation, no internal Faraday shield.	Limited to lower-power inverters (<3 kW); requires external noise filtering for >20 kV/µs dV/dt environments.	Select when cost sensitivity outweighs CMTI requirement and system dV/dt remains <20 kV/µs.
SI8271BD-D-IS	Si-based digital isolator with integrated gate driver, 4 A peak, 130 ns propagation, 5000 Vrms, no optical aging concerns.	Higher radiation tolerance and longer lifetime than LED-based couplers; requires separate 5 V logic supply and gate resistor tuning.	Prefer for long-life industrial systems (>15 yr MTBF) or where LED degradation over time is unacceptable.

Compared with ACPL-332J-500E and SI8271BD-D-IS, the TLP5754(LF4,E) uniquely combines reinforced 5000 Vrms isolation, ±4 A drive strength, and guaranteed ±35 kV/µs CMTI in a single SO6L package - making it optimal for compact, high-reliability inverter gate drive where optical coupling and extreme noise immunity are jointly required.

Availability

TLP5754(LF4,E) is available at Aetrix Electronics and suitable for induction cooktops, air conditioner inverters, and industrial motor drives requiring stable component supply, long-term lifecycle support, and certified safety compliance.

Supply support for TLP5754(LF4,E) includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Toshiba Electronic Devices & Storage Corporation is a Japanese semiconductor manufacturer specializing in power devices, logic ICs, and optoelectronics, with global manufacturing and quality certifications including ISO 9001 and IATF 16949.

The TLP5754(LF4,E) belongs to Toshiba's high-speed photocoupler product line, engineered specifically for noise-immune gate driving in energy-efficient inverters used in home appliances and industrial automation - prioritizing safety certification, thermal robustness, and layout efficiency.

FAQ

What is the maximum recommended operating temperature for the TLP5754(LF4,E)?

The TLP5754(LF4,E) is rated for continuous operation from –40°C to +110°C. This extended range supports deployment in sealed inverter enclosures and under-hood-adjacent environments where ambient temperatures exceed 85°C. Derating is not required within this range, and all electrical characteristics - including propagation delay and output current - are specified across the full –40°C to +110°C span per the datasheet.

Does the TLP5754(LF4,E) require an external bypass capacitor, and if so, what are the placement requirements?

Yes, the TLP5754(LF4,E) requires a 1 µF ceramic bypass capacitor between Pin 6 (VCC) and Pin 4 (GND). Per Toshiba's design guidance, this capacitor must be placed within 1 cm of both pins to ensure stable high-gain amplifier operation and prevent oscillation or erratic switching. Failure to meet this placement rule may result in unreliable output transitions or latch-up under load.

What safety certifications does the TLP5754(LF4,E) hold, and which standards do they cover?

The TLP5754(LF4,E) holds UL 1577 (File No. E67349), cUL CSA Component Acceptance (File No. E67349), VDE EN IEC 60747-5-5, EN IEC 62368-1, and CQC GB4943.1 certifications. These validate its reinforced insulation performance for use in mains-connected equipment, including induction cooktops and HVAC inverters sold in North America, Europe, Japan, Thailand, and China.

Can the TLP5754(LF4,E) drive SiC MOSFETs directly, and what gate resistance is recommended?

The TLP5754(LF4,E) can drive SiC MOSFETs directly due to its ±4.0 A peak output current and rail-to-rail VO swing. For typical 650 V SiC devices with 5–10 nF gate charge, a series gate resistor of 2.2–4.7 Ω is recommended to balance switching speed and ringing suppression. Layout must minimize loop inductance between VO, gate, and source to preserve the device's ±35 kV/µs CMTI advantage.

What is the function of Pin 2 (N.C.) on the TLP5754(LF4,E), and how should it be handled on the PCB?

Pin 2 on the TLP5754(LF4,E) is a no-connect (N.C.) terminal - internally unconnected and electrically isolated. It must remain unconnected on the PCB: no trace routing, no solder mask opening, and no copper pour beneath it. Connecting or routing to Pin 2 risks compromising internal isolation integrity and voiding safety certifications.

TLP5754(LF4,E Specifications

Product attributes: Attribute value

Manufacturer:: Toshiba Semiconductor and Storage

Series:: -

Package/Case:: 6-SOIC (0.295", 7.50mm Width)

Packaging:: Tube

Product Status:: Active

Technology:: Optical Coupling

Number of Channels:: 1

Voltage - Isolation:: 5000Vrms

Common Mode Transient Immunity (Min):: 35kV/µs

Propagation Delay tpLH / tpHL (Max):: 150ns, 150ns

Pulse Width Distortion (Max):: 50ns

Rise / Fall Time (Typ):: 15ns, 8ns

Current - Output High, Low:: 3A, 3A

Current - Peak Output:: 4A

Voltage - Forward (Vf) (Typ):: 1.55V

Current - DC Forward (If) (Max):: 20 mA

Voltage - Output Supply:: 15V ~ 30V

Grade:: -

Qualification:: -

Operating Temperature:: -40°C ~ 110°C

Mounting Type:: Surface Mount

Supplier Device Package:: 6-SO

Approval Agency:: CQC, CSA, cUL, UL, VDE

TLP5754(LF4,E FAQ

1.How can I place an order for TLP5754(LF4,E through Aetrix?

Please submit a Request for Quotation (RFQ) for TLP5754(LF4,E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TLP5754(LF4,E reliable?

The price and inventory of TLP5754(LF4,E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TLP5754(LF4,E is usually 5 days.

3.What payment methods are accepted for TLP5754(LF4,E?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TLP5754(LF4,E transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TLP5754(LF4,E?

TLP5754(LF4,E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TLP5754(LF4,E order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TLP5754(LF4,E?

For technical support, including TLP5754(LF4,E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TLP5754(LF4,E requirements.

6.How does Aetrix verify that TLP5754(LF4,E is sourced from the original manufacturer or authorized distributors?

All TLP5754(LF4,E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TLP5754(LF4,E meets industry standards.

7.What is the process for return or replacement of TLP5754(LF4,E?

All TLP5754(LF4,E units undergo pre-shipment inspection (PSI). If there is an issue with TLP5754(LF4,E, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TLP5754(LF4,E part is unused and in its original packaging.

Return procedure for TLP5754(LF4,E:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…