Texas Instruments TLV320AIC28IRGZRG4
- Part No.:
- TLV320AIC28IRGZRG4
- Manufacturer:
- Texas Instruments
- Category:
- CODECS
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
TLV320AIC28IRGZRG4.pdf
- Description:
- IC STEREO AUDIO CODEC LP 48-VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,500
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TLV320AIC28IRGZRG4 from Texas Instruments is a low-power, highly integrated stereo audio DAC and mono audio ADC in a 48-pin QFN package, supporting up to 48 ksps sampling rate, delivering 95-dB SNR stereo playback and 98-dB SNR speaker output, with integrated 400-mW BTL loudspeaker driver, 32-Ω differential earpiece driver, and hardware AGC for dual microphone inputs - deployed in cellular smartphones and digital camcorders.
For engineers reviewing the TLV320AIC28IRGZRG4 datasheet, TLV320AIC28IRGZRG4 pinout, TLV320AIC28IRGZRG4 application, or TLV320AIC28IRGZRG4 equivalent, key selection considerations include its dual-mode audio interface (I²S/DSP), on-chip PLL for flexible clock generation, capless headphone output capability, battery voltage monitoring up to 6 V, and programmable 12-bit SAR ADC with temperature sensing.
Technical Context
The TLV320AIC28IRGZRG4 integrates independent stereo DAC and mono ADC paths with Σ-Δ modulation, configurable interpolation filters enabling high-fidelity playback at non-standard rates (e.g., 11.025 kHz via 4× upsampling to 44.1 kHz), and a fully programmable digital audio effects engine supporting bass/treble/EQ/de-emphasis processing. Its analog front-end includes two dedicated microphone bias generators (2.0/2.5/3.3 V selectable) with hardware AGC offering 0.5-dB step resolution across 59.5 dB range.
Audio data routing supports master/slave I²S, left/right-justified, and DSP serial formats with 16/20/24/32-bit word lengths; clocking is managed by an on-chip PLL accepting MCLK inputs from 1–100 MHz and generating precise audio clocks without external crystals. The device implements a virtual ground (VGND) output to enable capacitor-less headphone drive and includes dedicated detection circuitry for headset insertion, button press, and earpiece type identification.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ADC/DAC Resolution | 16/20/24/32-bit programmable - enables compatibility with legacy and high-resolution audio processors without format conversion. |
| Max Sampling Rate | 48 ksps - supports CD-quality audio streaming and real-time voice recording in portable devices. |
| Stereo DAC SNR | 95 dBA - ensures high-fidelity headphone playback with minimal audible noise floor in battery-powered systems. |
| Loudspeaker Output Power | 400 mW into 8 Ω (BTL) - drives small speakers directly from battery supply (BVDD up to 4.2 V), eliminating external amplifiers. |
| Mic Input AGC Range | 0–59.5 dB in 0.5-dB steps - maintains consistent recording level across varying acoustic environments without host CPU intervention. |
| Battery Monitor Input | 0.5–6.0 V range with ±15 mV accuracy - enables precise state-of-charge estimation using single-ended analog input, no external divider needed. |
| SAR ADC Resolution | Programmable 8/10/12-bit - allows trade-off between measurement speed (up to 1 MSPS) and precision for auxiliary sensing tasks. |
| Supply Current (Playback) | 19 mW total at 48 ksps, 3.3-V analog supply - extends battery life in always-on audio applications such as voice assistants. |
Pinout & Package
TLV320AIC28IRGZRG4 is housed in a 7 × 7 mm, 48-pin QFN package with exposed thermal pad (RGZ designation), rated for −40°C to +85°C operation. Pin functions are validated per TI SLAS418B datasheet Rev. May 2005.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (IOVDD) | IO power supply | Supplies 1.1–3.6 V to SPI interface and digital I/Os; decoupling required for noise-sensitive audio timing. |
| 2 (PWR_DN) | Hardware power-down control | Active-low signal enabling full chip shutdown with 27 µA standby current; critical for ultra-low-power headset detection mode. |
| 3 (RESET) | Hardware reset input | Asynchronous active-low reset that clears all registers and reinitializes internal state machines - required before configuration sequence. |
| 25 (MIC_DETECT_IN) | Microphone detect input | Monitors headset jack continuity to trigger automatic detection of plug insertion/removal and initiate bias/gain reconfiguration. |
| 26 (OUT32N) | Differential earpiece output (−) | Paired with SPK1 (OUT32P) to deliver 82 mW into 32 Ω; supports telephone-grade receiver drive without external components. |
| 27 (SPK1) | Differential earpiece output (+) | Positive terminal of 32-Ω driver; used with OUT32N for balanced earpiece output or as mono headset driver output. |
| 28 (SPK2) | Headset driver output | Second 16-Ω headphone channel output; supports stereo capless configuration when paired with VGND (Pin 31). |
| 29 (DRVDD) | Headphone driver supply | 3.0–3.6 V analog supply for headphone amplifiers; separate from BVDD to isolate sensitive audio paths from battery ripple. |
| 31 (VGND) | Virtual ground reference | 1.5-V buffered output enabling capacitor-less headphone coupling - eliminates bulky DC-blocking caps and saves PCB space. |
| 34 (BVDD) | Battery supply input | Accepts 3–4.2 V direct battery connection; powers loudspeaker driver and enables 400-mW output without boost converter. |
| 35–36 (OUT8P/OUT8N) | Differential loudspeaker outputs | BTL configuration delivering 400 mW into 8 Ω; requires external LC filter for EMI compliance in handheld RF environments. |
| 43–44 (SDOUT/SDIN) | AUDIO serial data I/O | I²S/DSP-format bidirectional audio data lines; support 16–32-bit words and master/slave clocking for SoC integration. |
| 45–46 (WCLK/BCLK) | AUDIO word/bit clock | Configurable as inputs (slave) or outputs (master); WCLK defines sample rate, BCLK determines bit transfer timing. |
| 47 (MCLK) | Master clock input | Accepts 1–100 MHz crystal or oscillator input; feeds PLL to generate precise audio clocks - eliminates need for multiple crystals. |
| 48 (DVSS) | Digital ground | Common return for DVDD and IOVDD; must be isolated from analog grounds (AVSS1/AVSS2) except at single-point star ground. |
Key Features
| Feature | Design Value |
|---|---|
| Capless headphone output | VGND (Pin 31) provides stable 1.5-V reference enabling direct-coupled 16-Ω drive - removes 2× 220-µF electrolytic capacitors per channel. |
| Integrated PLL clock generator | Derives precise audio clocks (e.g., 44.1/48 kHz) from wide-range MCLK (1–100 MHz) - eliminates external crystal and reduces BOM count. |
| Hardware AGC with 0.5-dB steps | 59.5-dB dynamic range gain control applied in analog domain before ADC - preserves SNR while adapting to speech/mic distance changes. |
| Multi-function SAR ADC | 12-bit resolution with programmable averaging, timing, and 0.3°C temperature sensor - replaces discrete sensing ICs in space-constrained designs. |
| Headset auto-detection logic | Dedicated MIC_DETECT_IN (Pin 25) and GPIO-driven detection block - enables plug-and-play headset support without host polling overhead. |
| Direct battery voltage monitoring | 0.5–6.0 V input (VBAT, Pin 15) with ±15 mV accuracy - supports accurate fuel gauging using internal reference, no external resistor divider. |
Applications
| Smartphone Voice Call Path | Digital Camcorder Audio Capture |
|---|---|
|
Use Scenario: Full-duplex cellular call with simultaneous headset mic input and loudspeaker playback in noisy environments. IC Role / Device Role / Timing Role: TLV320AIC28IRGZRG4 acts as primary audio codec, handling mono mic ADC (with hardware AGC), stereo DAC playback, and BTL speaker drive - synchronized via shared MCLK and PLL-generated WCLK/BCLK. Use Value: 59.5-dB AGC maintains intelligible voice capture despite varying proximity; 400-mW speaker output enables hands-free mode without external amplifier; capless headphone output reduces component count. |
Use Scenario: High-fidelity stereo audio recording during video capture with automatic gain adjustment and battery telemetry. IC Role / Device Role / Timing Role: TLV320AIC28IRGZRG4 serves as audio front-end, digitizing stereo line-in or mic signals at 48 ksps while measuring battery voltage and board temperature concurrently. Use Value: 95-dB DAC SNR ensures clean monitor playback; programmable interpolation preserves fidelity at variable frame-rate audio sync; integrated SAR ADC eliminates separate fuel gauge IC. |
| MP3 Player with Headset Detection | PDA Audio Subsystem |
|
Use Scenario: Portable music player that automatically switches between speaker and headphone output upon jack insertion. IC Role / Device Role / Timing Role: TLV320AIC28IRGZRG4 performs stereo DAC playback, detects headset presence via MIC_DETECT_IN, and configures VGND-based capless drive - all under autonomous hardware control. Use Value: Zero-latency plug detection enables instant audio path reconfiguration; 19-mW playback power extends battery runtime; integrated keyclick generator provides tactile UI feedback. |
Use Scenario: Industrial PDA requiring voice memo recording, audio playback, and environmental monitoring in a single compact module. IC Role / Device Role / Timing Role: TLV320AIC28IRGZRG4 functions as unified audio and sensing hub - digitizing voice input, driving piezo buzzer (BUZZ_IN), reading AUX1/AUX2 sensors, and reporting temperature via SAR ADC. Use Value: Single-chip consolidation replaces discrete ADC, audio codec, and temp sensor; GPIO1/GPIO2 support custom peripheral control; low 50-µA deep-sleep current enables long-term logging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar audio codec applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TLV320AIC3106IRGZR | Lower power (12 mW playback), 96-dB DAC SNR, but lacks 400-mW speaker driver and battery monitor input. | Targeted at ultra-portable wearables where speaker output and battery telemetry are unnecessary. | Select when system uses external Class-D amplifier and relies on PMIC for battery sensing. |
| PCM3168APFPR | 8-channel audio interface, higher SNR (110 dB), but requires external clock source and has no integrated AGC or headset detection. | Suitable for multi-mic array recording in smart speakers, not mobile handsets with space/power constraints. | Choose only if application demands >2-channel I/O and can accommodate larger QFP package and external clock tree. |
Compared with TLV320AIC3106IRGZR and PCM3168APFPR, the TLV320AIC28IRGZRG4 uniquely combines high-efficiency speaker drive, autonomous headset detection, and battery monitoring in a single 7×7 mm QFN - making it optimal for cost- and size-sensitive mobile audio endpoints where integration reduces bill-of-materials and layout complexity.
Availability
TLV320AIC28IRGZRG4 is available at Aetrix Electronics and suitable for cellular smartphones, digital camcorders, MP3 players, and PDAs requiring stable component supply with guaranteed long-term manufacturability and automotive-grade temperature support.
Supply support for TLV320AIC28IRGZRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with over 50 years of innovation in precision signal chain solutions.
The TLV320AIC28IRGZRG4 belongs to TI's low-power audio codec product line, designed specifically for portable consumer electronics requiring high-fidelity audio, intelligent power management, and system-level integration of sensing and interface functions.
FAQ
What audio data formats does the TLV320AIC28IRGZRG4 support?
The TLV320AIC28IRGZRG4 supports I²S, left-justified, right-justified, and DSP serial audio formats with 16-, 20-, 24-, or 32-bit word lengths. It operates in master or slave mode, with clock direction (WCLK/BCLK as input or output) controlled by register bit D11 in page 2 register 06h. This flexibility allows seamless integration with diverse host processors including ARM-based SoCs and DSPs.
Does the TLV320AIC28IRGZRG4 support capacitor-less headphone output?
Yes, the TLV320AIC28IRGZRG4 supports capless headphone output via its dedicated VGND pin (Pin 31), which provides a stable 1.5-V reference. When used with SPK1 and SPK2 outputs, this eliminates the need for large DC-blocking electrolytic capacitors - reducing PCB area, cost, and potential failure points in portable designs.
How does the hardware AGC function in the TLV320AIC28IRGZRG4?
The TLV320AIC28IRGZRG4 implements analog-domain hardware AGC on both MICIN_HED and MICIN_HND inputs, offering 0–59.5 dB gain control in 0.5-dB steps. It operates autonomously without host CPU involvement, maintaining consistent recording levels across varying acoustic conditions - critical for reliable voice capture in smartphones and PDAs.
Can the TLV320AIC28IRGZRG4 measure battery voltage directly?
Yes, the TLV320AIC28IRGZRG4 includes a dedicated VBAT input (Pin 15) that accepts 0.5–6.0 V, enabling direct battery voltage monitoring with ±15 mV accuracy after system calibration. This feature eliminates the need for external resistor dividers and supports accurate fuel gauging in battery-powered devices.
What is the thermal management requirement for the TLV320AIC28IRGZRG4 loudspeaker driver?
When driving high power into an 8-Ω load for extended periods above 80°C ambient, the TLV320AIC28IRGZRG4 requires multiple vias connecting its exposed thermal pad to an internal ground plane. Its QFN package has θJA = 27°C/W with proper thermal pad soldering - ensuring safe junction temperature (TJ ≤ 105°C) during 400-mW continuous output.
TLV320AIC28IRGZRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Active
- Type:
- Stereo Audio
- Data Interface:
- Serial
- Resolution (Bits):
- 24 b
- Number of ADCs / DACs:
- 1 / 2
- Sigma Delta:
- Yes
- S/N Ratio, ADCs / DACs (db) Typ:
- 90 / 95
- Dynamic Range, ADCs / DACs (db) Typ:
- -
- Voltage - Supply, Analog:
- 3V ~ 3.6V
- Voltage - Supply, Digital:
- 1.65V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-VQFN (7x7)
TLV320AIC28IRGZRG4 FAQ
1.How can I place an order for TLV320AIC28IRGZRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for TLV320AIC28IRGZRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TLV320AIC28IRGZRG4 reliable?
The price and inventory of TLV320AIC28IRGZRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TLV320AIC28IRGZRG4 is usually 5 days.
3.What payment methods are accepted for TLV320AIC28IRGZRG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TLV320AIC28IRGZRG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TLV320AIC28IRGZRG4?
TLV320AIC28IRGZRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TLV320AIC28IRGZRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TLV320AIC28IRGZRG4?
For technical support, including TLV320AIC28IRGZRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TLV320AIC28IRGZRG4 requirements.
6.How does Aetrix verify that TLV320AIC28IRGZRG4 is sourced from the original manufacturer or authorized distributors?
All TLV320AIC28IRGZRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TLV320AIC28IRGZRG4 meets industry standards.
7.What is the process for return or replacement of TLV320AIC28IRGZRG4?
All TLV320AIC28IRGZRG4 units undergo pre-shipment inspection (PSI). If there is an issue with TLV320AIC28IRGZRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TLV320AIC28IRGZRG4 part is unused and in its original packaging.
Return procedure for TLV320AIC28IRGZRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TLV320AIC28IRGZRG4 Tags

-
NAU88C22YG
Nuvoton Technology Corporation

-
TLV320AIC3100IRHBR
Texas Instruments

-
DA7212-01UM2
Renesas

-
NAU8810YG
Nuvoton Technology Corporation

-
DA7218-00U32
Renesas

-
CMX655DQ6-TR1K
CML Micro

-
SGTL5000XNLA3
NXP Semiconductors

-
TLV320AIC3104IRHBR
Texas Instruments

-
MAX9867EWV+T
Analog Devices Inc./Maxim Integrated

-
MAX9860ETG+T
Analog Devices Inc./Maxim Integrated

-
TLV320AIC3106IRGZR
Texas Instruments

-
SGTL5000XNLA3R2
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
