Texas Instruments TLV5590ED

Overview

TLV5590ED from Texas Instruments is a 2-bit analog-to-digital converter optimized for FLEX protocol pagers, integrating dual-bandwidth (1 kHz/2 kHz ±5% −3 dB) 3rd-order Butterworth filtering, peak/valley detection with auto-adjusting 8-bit DACs, and four selectable acquisition modes - all operating from a single 2.7-V to 3.3-V supply. It directly interfaces with the TLV5591BVF FLEX decoder in numeric/alphanumeric pager baseband signal conditioning.

For engineers reviewing the TLV5590ED datasheet, TLV5590ED pinout, TLV5590ED application, or TLV5590ED equivalent, key selection considerations include its dual-bandwidth filter selectability via BW pin, real-time 2-bit ADC output on EXTS0/EXTS1, TRACKINH-controlled peak/valley tracking enable, and standby mode drawing only 1 µA - critical for battery-powered one-way/two-way pager designs.

Technical Context

The TLV5590ED implements a mixed-signal architecture where a switched-capacitor 3rd-order Butterworth filter precedes a 2-bit ADC whose reference levels (Vref+/Vref−) are dynamically set by two independent 8-bit DACs driven by up/down counters. Filter cutoff is digitally selected between 1 kHz and 2 kHz via the BW input, with nominal gain of 12 dB.

Its digital control logic latches all inputs (CON1, CON2, BW, TRACKINH, TEST) on the falling edge of a 38.4-kHz TTL-level CLK, enabling four operational modes: fast acquisition (attack rate 1.6–2.0 V/s), slow acquisition (0.8–1.0 V/s), hold (DAC outputs frozen), and standby (1 µA quiescent current). Peak/valley tracking is gated by TRACKINH, and decay timing is controlled by dedicated counters reset to 1 or 40 depending on mode.

Key Specifications

Pinout & Package

D-package (SOIC-14) surface-mount package with 14-pin dual in-line configuration, 1.27 mm pitch, body width 3.9 mm, and JEDEC MS-012AC compliance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar analog-to-digital signal conditioning applications.

Compared with TLV5590ED, TLV5590IDR offers wider temperature resilience at identical cost and footprint, while TLV5590EPR trades miniaturization for assembly flexibility - neither is pin-compatible with non-TLV5590 family devices, and both retain the same FLEX-specific filter/ADC architecture.

Availability

TLV5590ED is available at Aetrix Electronics and suitable for FLEX protocol numeric pagers, alphanumeric pagers, and one-way/two-way paging system front-ends requiring stable component supply, long-lifecycle support, and guaranteed traceable sourcing.

Supply support for TLV5590ED includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with over 50 years of innovation in precision signal chain components.

The TLV5590ED belongs to TI's legacy pager interface product line, designed specifically to reduce system cost and complexity in FLEX-standard wireless messaging devices by integrating filtering, detection, and digitization functions into a single IC.

FAQ

What is the primary function of the TLV5590ED in a FLEX pager system?

The TLV5590ED serves as the analog front-end signal conditioner and 2-bit ADC for FLEX protocol pagers. It receives the 4-level baseband audio signal from the receiver IF stage, applies selectable 1 kHz or 2 kHz filtering, performs automatic peak and valley detection using integrated 8-bit DACs, and outputs synchronized 2-bit digital data on EXTS0 and EXTS1 for decoding by the TLV5591BVF. Its design eliminates external passive components and firmware-based envelope tracking, making it essential to the TLV5590ED-based pager architecture.

How does the TLV5590ED achieve automatic reference level adjustment without external capacitors?

The TLV5590ED achieves capacitorless reference adjustment using two 8-bit DACs controlled by up/down counters that continuously monitor the filtered signal (FILOUT) and update Vref+ and Vref− in real time. The peak counter increments when the signal exceeds the current Vref+, and the valley counter decrements when the signal falls below Vref−. Attack and decay rates are determined by the CLK frequency and mode settings (fast/slow), eliminating the need for external hold capacitors while maintaining stability across temperature and supply variations - a core feature of the TLV5590ED architecture.

What are the voltage requirements and power consumption characteristics of the TLV5590ED?

The TLV5590ED operates from a single 2.7-V to 3.3-V supply on both DVDD and AVDD pins, with recommended ripple below 2 mVpp. In fast/slow/hold modes, it draws 250 µA typical supply current; in standby mode, it consumes only 1 µA - verified at DVDD = 2.7–3.3 V and TA = −25°C to +85°C. The MID pin provides a buffered AVDD/2 reference (1.42–1.58 V at 3 V), and absolute maximum ratings limit supply to 6.5 V. These specifications make the TLV5590ED highly suitable for coin-cell or Li-ion powered pagers where efficiency and voltage headroom are critical.

Can the TLV5590ED be used outside of FLEX pager applications?

The TLV5590ED is specifically architected for FLEX protocol signal conditioning and is not recommended for general-purpose ADC or filtering applications. Its 2-bit resolution, fixed 38.4-kHz clock dependency, 1/2 kHz filter cutoffs, and comparator thresholds scaled to 50/256, 134/256, and 217/256 of the peak–valley range are all optimized for 4-level FLEX symbol decoding. While the peak/valley detection and dual-bandwidth filter could theoretically be repurposed, the lack of programmable gain, adjustable thresholds, or standard serial interface limits interoperability - the TLV5590ED functions correctly only within its intended FLEX ecosystem.

How does the TRACKINH pin affect TLV5590ED operation and what is its correct connection?

The TRACKINH pin disables or enables real-time updating of the peak and valley DAC outputs: when low, the counters actively track signal envelope changes; when high, DAC outputs are frozen and EXTS0/EXTS1 respond directly to SIG–DC OFFSET in real time. In standard FLEX systems, TRACKINH must be connected to the SYMCLK output of the TLV5591BVF decoder to synchronize tracking inhibition with symbol boundaries - preventing erroneous threshold shifts during data transitions. Leaving TRACKINH unconnected or floating may cause erratic DAC behavior, so proper tie-off is mandatory for stable TLV5590ED operation.