Texas Instruments TLV5590EDR

Overview

TLV5590EDR from Texas Instruments is a 2-bit analog-to-digital converter with integrated 3rd-order Butterworth low-pass filter, peak/valley detectors, and dual-bandwidth selection (1 kHz ±5% or 2 kHz ±5%). It operates on a single 2.7–3.3 V supply, supports FLEX protocol pagers via direct interface to TLV5591 decoder, and delivers real-time 2-bit digital output (EXTS0/EXTS1) for 4-level baseband audio signals.

For engineers reviewing the TLV5590EDR datasheet, TLV5590EDR pinout, TLV5590EDR application, or TLV5590EDR equivalent, key selection considerations include its selectable dual-bandwidth filtering, zero-external-capacitor peak/valley detection, fast/slow/hold/standby mode control, 38.4 kHz clock-synchronized operation, and dedicated FLEX pager signal conditioning architecture.

Technical Context

The TLV5590EDR implements a mixed-signal signal chain: an analog input path (SIG–DC OFFSET differential front-end) feeds into a switched-capacitor 3rd-order Butterworth filter with digitally selectable 1 kHz or 2 kHz −3 dB cutoff, followed by peak/valley detection using two 8-bit DACs in feedback loops that dynamically set Vref+ and Vref− for the 2-bit ADC. The ADC uses three switched-capacitor comparators with thresholds defined by capacitor ratios and 50/256, 134/256, 217/256 fractions of the peak–valley span.

Digital control is fully synchronous to the 38.4 kHz TTL-level CLK input (edge-sensitive in normal modes), with BW, CON1, CON2, TRACKINH, and TEST inputs latched on the falling edge. Four operational modes-fast acquisition (attack rate 1.62–1.98 V/ms), slow acquisition (0.81–0.99 V/ms), hold, and standby (1 µA supply current)-are selected via CON1/CON2, while TRACKINH independently enables/disables peak/valley counter tracking without affecting decay timing.

Key Specifications

Pinout & Package

TLV5590EDR is housed in a 14-pin SOIC (D package), 1.75 mm body width, with standard JEDEC MS-012AC outline and 1.27 mm pitch. Pin numbering follows top-view convention with Pin 1 at bottom-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-bit ADC with integrated signal conditioning applications.

Compared with TLV5590ED and TLV5590IPW, the TLV5590EDR offers identical performance in the industry-standard SOIC-D package optimized for high-volume automated assembly, with verified tape-and-reel packaging for pick-and-place reliability and traceability.

Availability

TLV5590EDR is available at Aetrix Electronics and suitable for FLEX protocol pagers, one-way/two-way paging infrastructure, and battery-powered portable communication devices requiring stable component supply, long-lifecycle support, and consistent parametric performance across production batches.

Supply support for TLV5590EDR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and digital signal technologies, with decades of expertise in precision data converters and communications ICs.

The TLV5590EDR belongs to TI's legacy pager signal conditioning product line, designed specifically to reduce system cost and complexity in FLEX protocol implementations by integrating filtering, dynamic threshold generation, and 2-bit conversion in a single chip.

FAQ

What is the primary function of the TLV5590EDR in a FLEX pager system?

The TLV5590EDR serves as the analog front-end and 2-bit ADC for FLEX protocol pagers, directly interfacing with the TLV5591 decoder. It conditions the 4-level baseband audio signal using a selectable 1 kHz or 2 kHz Butterworth filter, dynamically tracks peak and valley levels with capacitorless DAC-based detectors, and outputs synchronized 2-bit digital data (EXTS0/EXTS1) for decoding. Its design eliminates external op-amps and hold capacitors, reducing BOM and board space in compact pager designs.

How does the TLV5590EDR achieve capacitorless peak and valley detection?

The TLV5590EDR achieves capacitorless peak and valley detection using two 8-bit DACs in closed-loop feedback configurations. Each DAC drives a comparator input, and up/down counters adjust the DAC codes based on signal amplitude relative to the DAC output. This architecture replaces traditional external hold capacitors with digital tracking, enabling precise, drift-free envelope detection without analog storage elements - a key innovation confirmed in the functional block diagram and Principles of Operation section of the SLAS134B datasheet.

What are the four operational modes of the TLV5590EDR and how are they selected?

The TLV5590EDR supports Fast Acquisition, Slow Acquisition, Hold, and Standby modes, selected jointly by CON1 and CON2 inputs per Table 1 in the datasheet: Low/Low = Standby, Low/High = Fast, High/Low = Hold, High/High = Slow. Fast mode provides rapid initial tracking (1.62–1.98 V/ms attack rate), Slow mode enables fine-grained synchronization (0.81–0.99 V/ms), Hold freezes DAC outputs during data transfers, and Standby reduces supply current to 1 µA. All modes are synchronized to the 38.4 kHz CLK input.

Can the TLV5590EDR operate with a supply voltage below 2.7 V?

No, the TLV5590EDR is not specified or guaranteed to operate below 2.7 V. The recommended operating conditions explicitly define a minimum supply voltage of 2.7 V for both AVDD and DVDD, and absolute maximum ratings caution against stresses beyond specifications. Operating below 2.7 V may cause degraded filter gain, increased DAC error, unreliable ADC thresholds, or failure to enter/exit standby mode correctly - all outside validated performance boundaries documented in the SLAS134B datasheet.

What is the role of the TRACKINH pin on the TLV5590EDR?

The TRACKINH pin on the TLV5590EDR controls real-time enable/disable of peak and valley detector counter updates. When TRACKINH is low, counters actively adjust DAC outputs to track signal envelope; when high, counters freeze while preserving their current state - effectively holding Vref+ and Vref− constant for the 2-bit ADC. In FLEX systems, TRACKINH is typically tied to the TLV5591's SYMCLK to synchronize tracking inhibition with decoder timing, preventing threshold shifts during critical data windows.