Texas Instruments TLV9104SIRTER
- Part No.:
- TLV9104SIRTER
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 16-WFQFN Exposed Pad
- Datasheet:
-
TLV9104SIRTER.pdf
- Description:
- IC OPAMP GP 4 CIRCUIT 16WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,648
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TLV9104SIRTER from Texas Instruments is a quad-channel, rail-to-rail input/output operational amplifier optimized for low-power, precision signal conditioning in space-constrained industrial and communications systems. It delivers 1.1-MHz gain-bandwidth, ±300 µV max input offset voltage, 120 µA per amplifier quiescent current, and operates from 2.7 V to 16 V supply. It serves as a high-accuracy, low-noise buffer and active filter stage in macro remote radio units (RRUs) and baseband units (BBUs).
For engineers reviewing the TLV9104SIRTER datasheet, TLV9104SIRTER pinout, TLV9104SIRTER application, or TLV9104SIRTER equivalent, this page provides verified package mapping (WQFN-16), confirmed shutdown control logic (SHDN12/SHDN34 active-high disable), exact channel count (4), and real-world performance boundaries including 4.5 V/µs slew rate, 28 nV/√Hz noise at 10 kHz, and –40°C to +125°C operation.
Technical Context
The TLV9104SIRTER integrates four independent amplifiers with matched AC/DC specifications across temperature. Its input stage supports rail-to-rail common-mode range (V– –0.2 V to V+ +0.2 V), enabling direct interfacing with ADCs and DACs operating near supply rails. The output stage drives ±80 mA and swings within 3 mV of rails under no-load conditions at 16 V.
It features dual independent shutdown controls: SHDN12 disables channels 1 and 2, SHDN34 disables channels 3 and 4 - each with 11 µs enable and 2.5 µs disable timing. The WQFN-16 package includes an exposed thermal pad connected to V–, reducing RθJA to 53.5°C/W and supporting stable operation at full ambient temperature range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain-bandwidth product | 1.1 MHz - supports stable unity-gain stable operation up to 10 kHz closed-loop bandwidth with minimal phase margin degradation. |
| Input offset voltage (max) | ±1.5 mV at 25°C - enables sub-12-bit DC accuracy without trimming in sensor front-ends and current-sense amplifiers. |
| Quiescent current per amp | 150 µA max - allows four-channel operation below 600 µA total, suitable for battery-backed instrumentation and portable test gear. |
| Slew rate | 4.5 V/µs - supports 10-V step response settling to 0.1% in 4 µs, sufficient for fast-settling anti-aliasing filters and pulse amplification. |
| Input voltage noise density | 28 nV/√Hz at 10 kHz - ensures <1 µV RMS integrated noise in 100-kHz bandwidth, critical for low-level analog signal integrity. |
| Common-mode rejection | 110 dB (typ) - rejects power-supply ripple and coupled interference in single-supply industrial I/O modules. |
| Supply voltage range | 2.7 V to 16 V - interoperates with both 3.3-V microcontrollers and 12-V industrial bus interfaces without level-shifting. |
| Operating temperature | –40°C to +125°C - qualified for under-hood automotive subsystems and outdoor telecom equipment enclosures. |
Pinout & Package
The TLV9104SIRTER is housed in a 3.0 mm × 3.0 mm, 16-pin WQFN package (RTE variant) with an exposed thermal pad soldered to V– for enhanced thermal dissipation. Pin 1 is marked by a dot; pin numbering follows standard counter-clockwise convention from top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | IN1– | Inverting input for amplifier channel 1 - referenced to system ground or virtual ground in differential configurations. |
| 2 | IN1+ | Noninverting input for amplifier channel 1 - accepts rail-to-rail signals from sensors or DAC outputs. |
| 3 | V+ | Positive supply rail - must be decoupled with ≥100 nF ceramic capacitor placed ≤2 mm from pin. |
| 4 | IN2+ | Noninverting input for amplifier channel 2 - electrically isolated from channel 1 inputs for multi-channel signal routing. |
| 5 | IN2– | Inverting input for amplifier channel 2 - supports independent feedback networks per channel. |
| 6 | OUT2 | Output for amplifier channel 2 - capable of sourcing/sinking ±80 mA into resistive loads or driving 20-pF capacitive loads stably. |
| 7 | OUT3 | Output for amplifier channel 3 - shares same drive strength and rail-swing capability as OUT1–OUT4. |
| 8 | IN3– | Inverting input for amplifier channel 3 - matches input bias current (±10 pA) and capacitance (6 || 1 TΩ || pF) across all channels. |
| 9 | IN3+ | Noninverting input for amplifier channel 3 - maintains ±0.6 µV/°C offset drift for stable DC performance over temperature. |
| 10 | V– | Negative supply rail - thermal pad must be soldered directly to this net for optimal junction-to-board thermal resistance (28.6°C/W). |
| 11 | IN4+ | Noninverting input for amplifier channel 4 - supports simultaneous multi-channel acquisition in data loggers and motor control feedback loops. |
| 12 | IN4– | Inverting input for amplifier channel 4 - fully specified for CMRR >90 dB across full common-mode range. |
| 13 | OUT4 | Output for amplifier channel 4 - exhibits identical small-signal overshoot and settling behavior as other outputs. |
| 14 | OUT1 | Output for amplifier channel 1 - connects to external load or next-stage input with minimal trace inductance to preserve 1.1-MHz bandwidth. |
| 15 | SHDN12 | Shutdown control for channels 1 & 2 - logic high (>V– + 1.1 V) disables both amplifiers; low ( |
| 16 | SHDN34 | Shutdown control for channels 3 & 4 - independent of SHDN12, enabling selective power gating in multi-function analog subsystems. |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail input and output | Supports full-scale signal swing from V– –0.2 V to V+ +0.2 V at input and within 3 mV of rails at output - eliminates need for level-shifting in single-supply designs. |
| Dual independent shutdown pins | SHDN12 and SHDN34 allow granular power management - reduces system-level quiescent current by >95% when only two channels are active. |
| Low input bias current (±10 pA) | Enables high-impedance sensor interfacing (e.g., pH electrodes, piezoresistive bridges) without significant DC error or signal loading. |
| Robust EMIRR (77 dB @ 1.8 GHz) | Rejects cellular and WiFi band RF interference in densely packed PCBs - prevents rectification-induced DC offset shifts in sensitive measurement paths. |
| Specified for –40°C to +125°C | Guarantees parametric performance across automotive under-hood and industrial control cabinet environments without derating. |
| Exposed thermal pad (V– connection) | Lowers junction-to-board thermal resistance to 28.6°C/W - sustains full 4-channel operation at 125°C ambient with ≤1.5 W total dissipation. |
Applications
| Optical Module Signal Conditioning | Portable Test & Measurement Front-End |
|---|---|
Use Scenario: Amplifying low-level photodiode current in SFP+ transceivers with minimal added noise and distortion. IC Role / Device Role / Timing Role: Transimpedance amplifier (TIA) stage and post-amplifier buffer for analog signal path before CDR circuitry. Use Value: 28 nV/√Hz input noise and 1.1-MHz GBW preserve signal integrity for 10-Gbps NRZ eye diagrams; rail-to-rail output drives 50-Ω transmission lines directly. |
Use Scenario: Multi-channel voltage/current measurement in handheld multimeters and oscilloscope probes. IC Role / Device Role / Timing Role: Precision buffer and programmable gain stage preceding SAR ADC sampling. Use Value: ±300 µV offset and ±0.6 µV/°C drift ensure <0.01% reading accuracy across battery-operated field use; 120 µA/amp extends runtime. |
| Macro Remote Radio Unit (RRU) | Baseband Unit (BBU) Analog Interface |
Use Scenario: Biasing and monitoring PA bias controllers and temperature compensation circuits in outdoor 4G/5G RRUs. IC Role / Device Role / Timing Role: Current-sense amplifier and temperature-sensor interface for FPGA-controlled RF front-end calibration. Use Value: 110 dB CMRR rejects switching noise from nearby DC-DC converters; –40°C to +125°C rating matches outdoor enclosure requirements. |
Use Scenario: Level-shifting and filtering I/Q analog signals between FPGA DACs and RF upconverters in indoor BBU chassis. IC Role / Device Role / Timing Role: Active low-pass filter and DC-coupled driver for complex baseband waveforms. Use Value: 4.5 V/µs slew rate supports clean 20-MHz LTE signal reconstruction; dual shutdown enables dynamic channel power-down during low-traffic periods. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad op-amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA491IDR | Higher GBW (4.5 MHz), higher IQ (120 µA/amp), no shutdown pins, SOIC-14 package only. | Better for wideband active filters but lacks power-gating capability; unsuitable where dynamic channel disabling is required. | Choose OPA491IDR when bandwidth >2 MHz is mandatory and shutdown is unnecessary. |
| LMV984MAX/NOPB | Lower supply range (1.8–5.5 V), lower IQ (110 µA/amp), no rail-to-rail output, SOIC-14 package. | Targeted at low-voltage portable devices only; cannot operate at 12 V or drive near supply rails - incompatible with industrial 12-V systems. | Choose LMV984MAX/NOPB only for 3.3-V-only battery-powered designs requiring minimal footprint. |
Compared with TLV9104SIRTER, OPA491IDR trades shutdown flexibility and rail-to-rail output for higher speed, while LMV984MAX/NOPB sacrifices supply range and output swing to reduce cost and IQ - making TLV9104SIRTER the sole option meeting 2.7–16 V, shutdown, rail-to-rail, and –40°C to +125°C requirements simultaneously.
Availability
TLV9104SIRTER is available at Aetrix Electronics and suitable for optical module manufacturing, portable test equipment production, and macro RRU/BBU deployment requiring stable component supply across extended temperature and long-lifecycle programs.
Supply support for TLV9104SIRTER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in precision op-amps and high-reliability industrial ICs.
The TLV910x family was designed specifically for low-power, high-precision signal conditioning in harsh-environment industrial, telecom, and instrumentation systems - emphasizing rail-to-rail operation, robust EMI immunity, and extended temperature qualification.
FAQ
What is the function of the SHDN12 and SHDN34 pins on the TLV9104SIRTER?
The SHDN12 pin controls power state for amplifier channels 1 and 2, while SHDN34 independently controls channels 3 and 4. Both are active-high inputs: applying a logic high (>V– + 1.1 V) disables the respective pair, reducing quiescent current to 20–30 µA per disabled amplifier. The TLV9104SIRTER achieves fast enable (11 µs) and disable (2.5 µs) transitions, enabling dynamic power management in multi-channel systems without disrupting adjacent channels.
Does the TLV9104SIRTER support true rail-to-rail output swing?
Yes, the TLV9104SIRTER delivers rail-to-rail output swing: at 16 V supply and no load, output voltage reaches within 3 mV of either rail; with 10-kΩ load, headroom increases to 45–60 mV. This capability allows direct interfacing with ADCs and digital logic without external level-shifting, preserving signal fidelity in single-supply industrial sensor nodes and data acquisition systems using the TLV9104SIRTER.
What is the maximum capacitive load the TLV9104SIRTER can drive stably?
The TLV9104SIRTER is characterized for stable operation with up to 20 pF capacitive load in unity-gain configuration, as verified by phase margin (≥60°) and overshoot measurements. Driving larger loads (e.g., >50 pF) requires isolation resistor or gain adjustment per TI's layout guidelines. This specification directly impacts TLV9104SIRTER use in PCB traces longer than 5 cm or when buffering multiple downstream inputs in analog signal distribution networks.
How does the TLV9104SIRTER handle electromagnetic interference in RF-dense environments?
The TLV9104SIRTER features 77 dB EMIRR (Electromagnetic Interference Rejection Ratio) at 1.8 GHz, meaning it attenuates cellular/WiFi band RF signals by 77 dB before they demodulate into DC offset errors. This is achieved via internal input-stage shielding and layout optimization - critical for TLV9104SIRTER deployment in optical modules and RRUs co-located with high-power RF transmitters where unmitigated EMI would corrupt precision analog measurements.
Is the thermal pad on the TLV9104SIRTER's WQFN package required to be connected?
Yes, the exposed thermal pad on the TLV9104SIRTER's WQFN-16 package must be soldered to the V– net on the PCB. Doing so reduces junction-to-board thermal resistance to 28.6°C/W and enables full 4-channel operation at 125°C ambient. Leaving the pad floating degrades thermal performance by >2×, risking thermal shutdown or parametric shift - a mandatory design requirement explicitly stated in TI's datasheet for reliable TLV9104SIRTER implementation.
TLV9104SIRTER Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Amplifier Type:
- General Purpose
- Number of Circuits:
- 4
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 4.5V/µs
- Gain Bandwidth Product:
- 1.1 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 10 pA
- Voltage - Input Offset:
- 300 µV
- Current - Supply:
- 115µA (x4 Channels)
- Current - Output / Channel:
- 80 mA
- Voltage - Supply Span (Min):
- 2.7 V
- Voltage - Supply Span (Max):
- 16 V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WQFN (3x3)
TLV9104SIRTER FAQ
1.How can I place an order for TLV9104SIRTER through Aetrix?
Please submit a Request for Quotation (RFQ) for TLV9104SIRTER on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TLV9104SIRTER reliable?
The price and inventory of TLV9104SIRTER are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TLV9104SIRTER is usually 5 days.
3.What payment methods are accepted for TLV9104SIRTER?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TLV9104SIRTER transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TLV9104SIRTER?
TLV9104SIRTER orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TLV9104SIRTER order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TLV9104SIRTER?
For technical support, including TLV9104SIRTER datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TLV9104SIRTER requirements.
6.How does Aetrix verify that TLV9104SIRTER is sourced from the original manufacturer or authorized distributors?
All TLV9104SIRTER products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TLV9104SIRTER meets industry standards.
7.What is the process for return or replacement of TLV9104SIRTER?
All TLV9104SIRTER units undergo pre-shipment inspection (PSI). If there is an issue with TLV9104SIRTER, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TLV9104SIRTER part is unused and in its original packaging.
Return procedure for TLV9104SIRTER:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TLV9104SIRTER Tags

-
LM358DT
STMicroelectronics

-
LM358DR
Texas Instruments

-
LM2904DR
Texas Instruments

-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments

-
MCP6006T-E/OT
Microchip Technology

-
MCP6006UT-E/OT
Microchip Technology

-
LM324PWR
Texas Instruments

-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments

-
LM358P
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
