Texas Instruments TMS320C6670ACYPA

Overview

TMS320C6670ACYPA from Texas Instruments is a multicore fixed- and floating-point system-on-chip (SoC) integrating eight C66x DSP cores, 4 MB of on-chip L3 SRAM, DDR3 memory controller, and KeyStone I architecture interconnect. It operates at up to 1.25 GHz per core, supports 64-bit DDR3-1333 interface, and delivers 160 GMACs/200 GFLOPS peak performance for radar, wireless infrastructure, and medical imaging signal processing.

For engineers reviewing the TMS320C6670ACYPA datasheet, TMS320C6670ACYPA pinout, TMS320C6670ACYPA application, or TMS320C6670ACYPA equivalent, key selection criteria include multicore DSP throughput, integrated DDR3 controller timing compliance, KeyStone fabric bandwidth allocation, and SmartReflex power management support in industrial temperature grade.

Technical Context

The TMS320C6670ACYPA implements KeyStone I architecture with TeraNet switch fabric enabling non-blocking communication between eight C66x cores, peripherals, and memory controllers. It features three independent PLLs-Main PLL (up to 1.25 GHz), DDR3 PLL (up to 667 MHz), and PASS PLL (for SerDes and HyperLink)-with programmable dividers and lock detection.

Memory subsystem includes 32 KB L1P + 32 KB L1D per core, 1 MB shared L2, and 4 MB unified L3 SRAM. Power management uses SmartReflex dynamic voltage and frequency scaling (DVFS), with PSC-controlled power domains and thermal monitoring via po_vcon_smpserr_intr event.

Key Specifications

Pinout & Package

FCBGA-1197 package with 1197 solder balls arranged in 35 × 35 array, 1.0 mm ball pitch, and thermal lid for efficient heat dissipation. Pinout validated per TI SPRS689D Section 2.6.2 (Pin Map) and Table 2-1 (Package Terminals).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multicore DSP applications.

Compared with TMS320C6670ACYPA, the C6678 offers higher interconnect bandwidth but larger footprint and cost, while the SC589 provides ARM software ecosystem access at the expense of deterministic DSP cycle count predictability and L3 capacity.

Availability

TMS320C6670ACYPA is available at Aetrix Electronics and suitable for radar signal processing, wireless infrastructure baseband, and medical ultrasound imaging requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for TMS320C6670ACYPA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company founded in 1930, specializing in analog, embedded processing, and digital signal processing technologies.

The TMS320C66x series targets high-performance signal processing in radar, communications, and imaging systems, emphasizing deterministic multicore execution, memory bandwidth, and industrial reliability.

FAQ

What is the maximum operating frequency of the TMS320C6670ACYPA?

The TMS320C6670ACYPA operates at a maximum core frequency of 1.25 GHz per C66x DSP core. This frequency is supported under recommended operating conditions (VDD_CORE = 1.0 V, TJ ≤ 100°C) and enables 160 GMACs/200 GFLOPS peak performance. The device's Main PLL must be configured with appropriate multiplier/divider settings to achieve this speed, and thermal management must ensure junction temperature remains within specification during sustained operation.

Does the TMS320C6670ACYPA support DDR3 memory, and what are its interface specifications?

Yes, the TMS320C6670ACYPA integrates a fully compliant DDR3 memory controller supporting 64-bit DDR3-1333 (667 MHz clock). It implements JEDEC-standard timing parameters, on-die termination, write leveling, and read-leveling calibration. The controller supports up to 8 GB addressable space and delivers up to 10.6 GB/s theoretical bandwidth, validated per TI SPRS689D Section 7.11.

How many C66x cores does the TMS320C6670ACYPA contain, and are they cache-coherent?

The TMS320C6670ACYPA contains eight C66x DSP cores. These cores are not cache-coherent at the L1/L2 level; coherence is managed at the L3 SRAM level through software-controlled memory barriers and explicit cache maintenance instructions. The KeyStone I TeraNet fabric ensures deterministic, low-latency access to shared L3 and peripherals, but cache coherency protocols like MESI are not implemented in hardware.

What power management features does the TMS320C6670ACYPA offer?

The TMS320C6670ACYPA includes SmartReflex dynamic voltage and frequency scaling (DVFS), Power Sleep Controller (PSC)-managed power domains, and thermal monitoring via the po_vcon_smpserr_intr SmartReflex event. It supports multiple low-power states per core and peripheral, with independent clock gating and power gating controlled through PSC registers. DVFS adjusts VDD_CORE in real time based on workload and temperature feedback.

Is the TMS320C6670ACYPA pin-compatible with other C66x-series devices such as the TMS320C6678?

No, the TMS320C6670ACYPA is not pin-compatible with the TMS320C6678 or other C66x-series devices. While both use FCBGA packages, the TMS320C6670ACYPA has 1197 balls in a 29 mm × 29 mm array, whereas the C6678 uses a 1388-ball FCBGA. Ball assignments, power rail distribution, and peripheral pin mappings differ significantly due to architectural differences-including absence of HyperLink and SRIO in the C6670-and require unique PCB layout.