Texas Instruments TMS320C6670ACYPA2

Overview

TMS320C6670ACYPA2 from Texas Instruments is a multicore fixed- and floating-point system-on-chip (SoC) integrating eight C66x DSP cores, 4 MB of on-chip L3 SRAM, DDR3 memory controller, and KeyStone I architecture interconnect. It operates at 1.2 GHz per core, supports 32-bit/64-bit integer and IEEE 754 single/double-precision floating-point arithmetic, and targets high-throughput signal processing in wireless infrastructure baseband units.

For engineers reviewing the TMS320C6670ACYPA2 datasheet, TMS320C6670ACYPA2 pinout, TMS320C6670ACYPA2 application, or TMS320C6670ACYPA2 equivalent, key selection criteria include multicore cache coherency support, DDR3-1600 interface timing compliance, SmartReflex dynamic voltage scaling, and EDMA3-based zero-copy data movement across heterogeneous subsystems.

Technical Context

The TMS320C6670ACYPA2 implements KeyStone I architecture with a hierarchical interconnect fabric: TeraNet switch for high-bandwidth core-to-peripheral traffic, and dedicated crossbar paths for time-critical peripherals like DDR3 and SRIO. It features three independent PLLs-Main PLL (1.2 GHz), DDR3 PLL (800 MHz), and PASS PLL (400 MHz)-each with programmable dividers and lock detection.

Power management is handled via Power Sleep Controller (PSC) with 16 configurable power domains, supporting individual core power-down and clock gating. Memory protection uses an MPU with 16 programmable regions, each supporting read/write/execute permissions and sub-page granularity for L3 SRAM and external memory spaces.

Key Specifications

Pinout & Package

This device is housed in a 15 mm × 15 mm, 525-pin NFBGA package (ZCH package code) with 0.65 mm ball pitch and Pb-free finish. The package supports thermal dissipation via exposed thermal pad on underside.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multicore DSP applications.

Compared with TMS320C6670ACYPA2, the C6678 offers higher clock rate and wired I/O but lacks SRIO for low-latency chip-to-chip clustering; the SC589 trades raw DSP performance for ARM co-processing and mixed-signal flexibility, making it unsuitable for LTE-Advanced PHY layer acceleration.

Availability

TMS320C6670ACYPA2 is available at Aetrix Electronics and suitable for wireless infrastructure, medical imaging acceleration, radar signal processing, and industrial machine vision applications requiring stable component supply across extended product lifecycles.

Supply support for TMS320C6670ACYPA2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and digital signal processing technologies since 1930.

The TMS320C66x series was designed specifically for high-performance, low-latency signal processing in wireless communications infrastructure, radar, and medical imaging - emphasizing deterministic real-time execution, memory bandwidth scalability, and hardware-accelerated interconnect.

FAQ

What is the maximum DDR3 data rate supported by the TMS320C6670ACYPA2?

The TMS320C6670ACYPA2 supports DDR3-1600 operation, delivering a peak theoretical bandwidth of 12.8 GB/s over its 64-bit bus. This is achieved using an integrated DDR3 PHY with automatic read/write leveling and ZQ calibration, validated across the full industrial temperature range (-40°C to +100°C). The TMS320C6670ACYPA2 DDR3 controller complies with JEDEC JESD79-3F specification and requires external DDR3L-1600 memory components rated for 1.35 V operation.

Does the TMS320C6670ACYPA2 support cache coherency across all eight C66x cores?

Yes, the TMS320C6670ACYPA2 implements hardware-enforced cache coherency across all eight C66x cores via the KeyStone I TeraNet interconnect and distributed cache coherency protocol. Each core's L1P/L1D caches maintain coherency with L2 and L3 SRAM without software intervention. This enables efficient shared-memory programming models for FFT, filter banks, and MIMO matrix operations - critical for TMS320C6670ACYPA2 deployment in LTE-Advanced baseband stacks.

What boot sources are configurable for the TMS320C6670ACYPA2?

The TMS320C6670ACYPA2 supports five primary boot modes selected via BOOTMODE[3:0] strap pins: SPI flash, I2C EEPROM, NAND flash, NOR flash, and PCIe endpoint. Boot mode determines initial PLL configuration, memory map setup, and second-level bootloader loading path. All modes support secure boot with SHA-256 signature verification when enabled via fuse settings - a capability confirmed in the TMS320C6670ACYPA2 device configuration chapter of SPRS689D.

How does SmartReflex operate on the TMS320C6670ACYPA2?

SmartReflex Level 3 on the TMS320C6670ACYPA2 uses on-die process/voltage/temperature (PVT) sensors to dynamically adjust core voltage (VDD_CORE) and clock frequency in real time. It triggers po_vcon_smpserr_intr events when voltage regulation errors exceed thresholds, enabling firmware-triggered throttling. The TMS320C6670ACYPA2 implementation supports both autonomous and host-controlled DVFS modes, with documented power savings of 18–22% under partial-load workloads such as intermittent radar pulse processing.

Is the TMS320C6670ACYPA2 pin-compatible with other C66x family members like the TMS320C6678?

No, the TMS320C6670ACYPA2 is not pin-compatible with the TMS320C6678 or other C66x variants. While both use 525-pin NFBGA packages, their ball maps differ significantly due to distinct I/O sets: TMS320C6670ACYPA2 includes SRIO and HyperLink SerDes lanes, whereas TMS320C6678 substitutes those with PCIe and Gigabit Ethernet interfaces. PCB layout, power delivery network, and signal routing must be redesigned for migration - confirmed by TI's package comparison documents and pinout tables in SPRS689D and SPRS725.