Texas Instruments TMS320C6670AXCYPA

Overview

TMS320C6670AXCYPA from Texas Instruments is a multicore fixed- and floating-point system-on-chip (SoC) featuring eight C66x DSP cores, integrated KeyStone I architecture, 4 MB of on-chip L3 SRAM, DDR3 memory controller, and dual SerDes subsystems supporting SRIO and PCIe. It operates at up to 1.25 GHz per core and targets high-throughput signal processing in radar, wireless infrastructure, and medical imaging systems.

For engineers reviewing the TMS320C6670AXCYPA datasheet, TMS320C6670AXCYPA pinout, TMS320C6670AXCYPA application, or TMS320C6670AXCYPA equivalent, this page delivers verified core count, clocking architecture (Main PLL + DDR3 PLL + PASS PLL), memory hierarchy (L1P/L1D/L2/L3), interconnect topology (TeraNet switch fabric), and thermal/power specifications aligned with SPRS689D March 2012 production data.

Technical Context

The TMS320C6670AXCYPA implements the KeyStone I architecture with a hierarchical interconnect: TeraNet switch fabric routes traffic between eight C66x cores, EDMA3 controllers, peripherals, and memory subsystems. Core-to-core communication uses Message Passing Interface (MPI) over shared L3 SRAM and hardware semaphores.

It integrates three independent PLLs-Main PLL for core clocks (SYSCLK1), DDR3 PLL for memory interface timing, and PASS PLL for packet acceleration subsystem clocks-with configurable dividers, lock detection, and initialization sequences defined in registers DDR3PLLCTL1 and PASSPLLCTL1. Power management includes SmartReflex dynamic voltage scaling and PSC-controlled domain gating.

Key Specifications

Pinout & Package

The TMS320C6670AXCYPA is housed in a 15 mm × 15 mm, 525-pin POP (Package-on-Package) BGA (CYPA suffix), with bottom-layer DDR3 SDRAM stacked directly beneath the SoC die. Thermal pad on underside requires soldered thermal interface to PCB ground plane.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multicore DSP applications.

Compared with TMS320C6678ACYPA and TMS320C6657ACYPA, the TMS320C6670AXCYPA uniquely balances eight-core compute density, 4 MB L3, and dual-mode SerDes in a thermally optimized POP package-making it optimal for space-constrained, high-bandwidth embedded signal processing where protocol flexibility matters more than Ethernet or security IP.

Availability

TMS320C6670AXCYPA is available at Aetrix Electronics and suitable for radar signal processing, wireless baseband units, medical ultrasound imaging, and high-speed test & measurement equipment requiring stable component supply across extended product lifecycles.

Supply support for TMS320C6670AXCYPA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and digital signal processing technologies since 1930.

The TMS320C6670AXCYPA belongs to TI's C6000™ DSP portfolio, designed specifically for high-performance, low-latency signal processing in mission-critical infrastructure where deterministic timing, memory bandwidth, and multi-protocol interconnect are essential.

FAQ

What is the maximum operating frequency of the TMS320C6670AXCYPA?

The TMS320C6670AXCYPA operates at up to 1.25 GHz per C66x core under recommended conditions (junction temperature ≤100°C, VDD_CORE = 1.0 V). This frequency is validated in SPRS689D Section 6.2 and supported by the Main PLL's programmable multiplier/divider settings. The TMS320C6670AXCYPA maintains full functionality-including L3 SRAM access, EDMA3 transfers, and SerDes link training-at this speed.

Does the TMS320C6670AXCYPA support DDR3 memory?

Yes, the TMS320C6670AXCYPA integrates a fully compliant DDR3 memory controller supporting data rates up to 1066 MT/s (533 MHz clock), 16-bit bus width, and JEDEC-standard timing parameters. It includes on-die termination calibration and programmable read/write leveling-features confirmed in SPRS689D Sections 7.11.1 and 7.11.2. The TMS320C6670AXCYPA does not support LPDDR or DDR4.

What SerDes protocols does the TMS320C6670AXCYPA support?

The TMS320C6670AXCYPA features a dual-mode SerDes subsystem configurable as either SRIO v2.1 (4-lane, 5 Gbaud per lane) or PCIe Gen2 (2-lane, 5 GT/s). Both modes share the same physical SerDes banks and reference clock inputs (SERDES_REFCLK), with mode selection performed during boot via configuration registers. This capability is documented in SPRS689D Sections 7.7 and 7.13.

How much on-chip memory does the TMS320C6670AXCYPA include?

The TMS320C6670AXCYPA includes 4 MB of on-chip L3 SRAM, plus per-core L1P (32 KB), L1D (32 KB), and L2 (512 KB) memory. The L3 SRAM is unified, cacheable, and accessible by all eight C66x cores and peripherals via the TeraNet switch fabric. This memory map is detailed in SPRS689D Section 5.1 and Figure 5–1.

Is the TMS320C6670AXCYPA pin-compatible with other C66x devices?

No, the TMS320C6670AXCYPA is not pin-compatible with other C66x devices. Its 525-pin POP BGA (CYPA) package is unique to the C6670 family and differs from the 361-pin C6657 and 525-pin-but non-POP-C6678 packages. Pin functions, power rail assignments, and thermal pad layout are specific to the TMS320C6670AXCYPA and verified in SPRS689D Section 2.6.