Texas Instruments TMS320C6670AXCYPA2

Overview

TMS320C6670AXCYPA2 from Texas Instruments is a multicore fixed- and floating-point system-on-chip (SoC) featuring eight C66x DSP cores, 4 MB of on-chip L3 memory, DDR3 memory controller, and integrated SerDes for SRIO/PCIe/HyperLink interfaces. It operates at up to 1.25 GHz per core and supports real-time signal processing in radar, wireless infrastructure, and medical imaging systems.

For engineers reviewing the TMS320C6670AXCYPA2 datasheet, TMS320C6670AXCYPA2 pinout, TMS320C6670AXCYPA2 application, or TMS320C6670AXCYPA2 equivalent, key selection criteria include multicore DSP throughput, DDR3 interface timing compliance, SerDes protocol flexibility (SRIO v2.1/PCIe Gen2/HyperLink), SmartReflex power management, and KeyStone architecture interconnect scalability.

Technical Context

The TMS320C6670AXCYPA2 implements the KeyStone I architecture with a non-blocking TeraNet switch fabric enabling concurrent access among eight C66x cores, EDMA3 controllers, peripherals, and memory subsystems. Its hierarchical memory includes L1P/L1D per core (32 KB each), unified 1 MB L2, and 4 MB shared L3 SRAM.

Three dedicated PLLs-Main PLL (up to 1.25 GHz), DDR3 PLL (up to 1066 MHz), and PASS PLL (for SerDes)-support independent domain clocking. The device integrates hardware accelerators including FFT, Viterbi, and CRC engines, and supports boot from NAND, SPI, I²C, or PCIe via configurable ROM bootloader.

Key Specifications

Pinout & Package

The TMS320C6670AXCYPA2 is housed in a 1296-ball flip-chip BGA (FCBGA) package with thermal lid and exposed die attach pad. Ball pitch is 1.0 mm; package dimensions are 29 mm × 29 mm × 2.4 mm (max). Thermal resistance θ_JA is 11.5°C/W under JEDEC JESD51-7 conditions.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multicore DSP SoC applications.

Compared with TMS320C6670AXCYPA2, the C6678 offers expanded I/O at the cost of reduced SerDes flexibility, while the ADSP-SC589 trades raw DSP throughput and interconnect capability for ARM+SHARC heterogeneity and lower power - making each suitable for distinct system-level trade-offs in infrastructure vs. embedded domains.

Availability

TMS320C6670AXCYPA2 is available at Aetrix Electronics and suitable for radar signal processing, wireless baseband units, medical ultrasound imaging, and test & measurement equipment requiring stable component supply across extended product lifecycles.

Supply support for TMS320C6670AXCYPA2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets since 1930.

The TMS320C6670AXCYPA2 belongs to TI's KeyStone I multicore DSP platform, designed specifically for high-throughput, low-latency signal processing in wireless infrastructure, defense radar, and medical imaging systems where deterministic performance and scalable interconnect are critical.

FAQ

What is the maximum operating frequency of the TMS320C6670AXCYPA2?

The TMS320C6670AXCYPA2 operates at a maximum core frequency of 1.25 GHz per C66x DSP core, as validated under recommended operating conditions (VDD_CORE = 1.0 V ±3%, junction temperature ≤ 100°C). This frequency enables ≥10 GFLOPS per core and supports real-time execution of computationally intensive algorithms such as 4096-point FFTs and turbo decoding in wireless baseband applications. The TMS320C6670AXCYPA2 achieves this performance using adaptive voltage scaling controlled by its SmartReflex subsystem.

Does the TMS320C6670AXCYPA2 support DDR3 memory interfaces?

Yes, the TMS320C6670AXCYPA2 integrates a fully compliant 16-bit DDR3 SDRAM controller supporting data rates up to 1066 MT/s (DDR3-1066). It includes programmable timing parameters (tRCD, tRP, tRAS), on-die termination (ODT), and write-leveling calibration to ensure signal integrity across varying board layouts and memory modules. The controller connects directly to external DDR3 chips without requiring external level shifters or buffers, simplifying system design for TMS320C6670AXCYPA2-based platforms.

What SerDes protocols does the TMS320C6670AXCYPA2 support?

The TMS320C6670AXCYPA2 supports three high-speed serial protocols via its integrated PASS PLL-controlled SerDes: SRIO v2.1 (4 lanes at 3.125 Gbps), PCIe Gen2 (2 lanes at 5 Gbps), and HyperLink (2 links at 5 Gbps). Each protocol uses separate lane groups with independent clocking and link training. The TMS320C6670AXCYPA2 does not support PCIe Gen3 or USB; configuration is done through PASSPLLCTL registers and SerDes status/config MMRs during initialization.

How many C66x DSP cores does the TMS320C6670AXCYPA2 contain?

The TMS320C6670AXCYPA2 contains eight identical C66x DSP cores, each with dual 32-bit MAC units, IEEE 754-compliant single- and double-precision floating-point units, and 32 KB L1P + 32 KB L1D cache. All cores share 4 MB of unified L3 SRAM and access peripherals via the TeraNet switch fabric. This eight-core configuration delivers ≥80 GMACs and ≥80 GFLOPS peak performance, making the TMS320C6670AXCYPA2 suitable for massively parallel signal processing workloads.

What boot sources are supported by the TMS320C6670AXCYPA2?

The TMS320C6670AXCYPA2 supports boot from NAND flash, SPI flash, I²C EEPROM, and PCIe root complex via a mask-ROM bootloader. Boot mode is selected using the 4-bit BOOTMODE[3:0] strap pins sampled at power-on reset. The ROM code validates image integrity using SHA-1 hash and decrypts encrypted payloads with AES-128 if enabled. Secondary bootloaders can then load application code into L2 or L3 memory before core release, ensuring secure and flexible startup for TMS320C6670AXCYPA2-based systems.