Texas Instruments TMS320C6670CYPA2

Overview

TMS320C6670CYPA2 from Texas Instruments is a multicore fixed- and floating-point system-on-chip (SoC) featuring eight C66x DSP cores, 4 MB of on-chip L3 SRAM, integrated DDR3 memory controller, and TeraNet switch fabric for high-bandwidth interconnect. It operates at up to 1.25 GHz per core, supports IEEE 754 single- and double-precision floating-point arithmetic, and targets radar processing, baseband wireless infrastructure, and high-performance embedded vision systems.

For engineers reviewing the TMS320C6670CYPA2 datasheet, TMS320C6670CYPA2 pinout, TMS320C6670CYPA2 application, or TMS320C6670CYPA2 equivalent, key selection criteria include multicore DSP throughput (80 GFLOPS peak), DDR3-1333 interface timing compliance, SmartReflex dynamic voltage scaling support, and JTAG-based debug capability across all eight cores.

Technical Context

The TMS320C6670CYPA2 implements the KeyStone I architecture with a hierarchical interconnect: eight C66x cores share L2 cache and connect via CorePac-level crossbar to the TeraNet switch fabric, which routes traffic between peripherals including DDR3, PCIe, SRIO, HyperLink, and multiple EDMA3 controllers. Memory coherency is maintained through hardware-managed snoop protocols across L1/L2 caches.

Its clocking subsystem includes three independent PLLs - Main PLL (for core/system clocks), DDR3 PLL (for DDR3 PHY interface), and PASS PLL (for SerDes/PCIe/SRIO) - each with programmable dividers, lock detection, and initialization sequences defined in dedicated control registers (e.g., MAINPLLCTL0, DDR3PLLCTL1, PASSPLLCTL1).

Key Specifications

Pinout & Package

The TMS320C6670CYPA2 is housed in a 15 mm × 15 mm, 525-pin PBGA package (ZAY suffix), with 1.0 mm ball pitch and RoHS-compliant finish. Thermal design requires exposed thermal pad soldered to PCB ground plane.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multicore DSP applications.

Compared with TMS320C6678ACYPA2 and TMS320C6657CZHA2, the TMS320C6670CYPA2 uniquely balances PCIe Gen2 + SRIO + DDR3 integration with scalable 8-core DSP performance - making it optimal for next-generation wireless infrastructure requiring both high I/O flexibility and deterministic compute.

Availability

TMS320C6670CYPA2 is available at Aetrix Electronics and suitable for radar processing, wireless infrastructure, medical imaging, and industrial machine vision applications requiring stable component supply and long-term industrial lifecycle support.

Supply support for TMS320C6670CYPA2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets.

The TMS320C6670CYPA2 belongs to TI's KeyStone I multicore DSP platform, designed specifically for high-throughput, low-latency signal processing in radar, wireless infrastructure, and real-time imaging systems.

FAQ

What is the maximum operating frequency of the TMS320C6670CYPA2?

The TMS320C6670CYPA2 operates at a maximum core frequency of 1.25 GHz per C66x DSP core, confirmed in the SPRS689D datasheet Section 2.1 (Device Characteristics). This frequency is achieved under recommended operating conditions (1.05 V core supply, 85°C junction temperature) and enables 80 GFLOPS peak single-precision performance. The TMS320C6670CYPA2 uses separate PLLs for core, DDR3, and SerDes domains, allowing independent scaling of each clock domain.

Does the TMS320C6670CYPA2 support PCIe Gen2?

Yes, the TMS320C6670CYPA2 supports PCIe Gen2 (5 GT/s) via its integrated SerDes lanes configured as PCIe endpoints, as documented in Section 7.7 (PASS PLL) and Section 7.11 (SerDes configuration) of SPRS689D. It requires external PCIe reference clock (100 MHz differential) on PCIe_REFCLK± pins and complies with PCIe Base Specification 2.0 electrical requirements, including transmitter jitter (≤1.0 ps RMS) and receiver equalization.

How much on-chip memory does the TMS320C6670CYPA2 include?

The TMS320C6670CYPA2 integrates 4 MB of unified on-chip L3 SRAM, accessible by all eight C66x cores and peripherals via the TeraNet fabric. This memory is distinct from core-private L1P/L1D (32 KB each) and shared L2 (1 MB total). The 4 MB L3 is configurable as cache or scratchpad and does not require external DRAM for boot or real-time buffer storage, reducing system latency and BOM cost.

What debug interfaces are supported by the TMS320C6670CYPA2?

The TMS320C6670CYPA2 supports IEEE 1149.1 JTAG for boundary scan and multi-core debug, with full visibility into all eight C66x cores' registers, program counters, and memory spaces. It also supports SWD (Serial Wire Debug) via dedicated pins and includes Nexus Class 3+ trace capability with 1 ns output skew, enabling cycle-accurate instruction tracing across all cores simultaneously.

Is the TMS320C6670CYPA2 pin-compatible with other C66x-based devices?

No, the TMS320C6670CYPA2 is not pin-compatible with other C66x-based devices such as the TMS320C6678 or TMS320C6657. Its 525-ball PBGA (ZAY) package has unique ball map, power rail assignments (e.g., separate VDD_CORE, VDD_DDR, VDD_PCIE), and peripheral pinouts (e.g., dedicated SRIO lanes not shared with PCIe). Migration requires PCB redesign and firmware adaptation due to differences in memory map, interrupt controller (CIC vs. INTC), and boot ROM behavior.