Texas Instruments TMS320C6713BZDP300

Overview

TMS320C6713BZDP300 from Texas Instruments is a 300-MHz floating-point digital signal processor (DSP) based on the C67x VLIW architecture, delivering 2400 MIPS and 1800 MFLOPS. It integrates dual McASPs for multichannel audio I/O, 256 KB on-chip L2 memory (64 KB cache/mapped RAM + 192 KB SRAM), and a glueless 32-bit EMIF supporting SDRAM and Flash - deployed in professional audio processing systems requiring real-time multi-format digital audio handling.

For engineers reviewing the TMS320C6713BZDP300 datasheet, TMS320C6713BZDP300 pinout, TMS320C6713BZDP300 application, or TMS320C6713BZDP300 equivalent, key selection criteria include its 272-ball BGA (ZDP) package, IEEE 754 single/double-precision support, McASP DIT compliance with S/PDIF/IEC60958, and 1.2-V core / 3.3-V I/O voltage configuration at 300 MHz operation.

Technical Context

The TMS320C6713BZDP300 implements an eight-functional-unit VLIW CPU with two fixed-point ALUs, four floating-/fixed-point ALUs, and two floating-/fixed-point multipliers - enabling parallel execution of eight 32-bit instructions per cycle. Its L1/L2 memory hierarchy includes 4 KB direct-mapped L1P, 4 KB 2-way L1D, and 256 KB unified L2 space partitioned into configurable cache and mapped RAM.

Peripherals are clocked independently: McASPs use AUXCLK for high-frequency serial transfers and SYSCLK2 for clock-check logic; EMIF operates at SYSCLK3 or ECLKIN; HPI runs at SYSCLK2. The device supports little- and big-endian boot modes via HD[4:3] and CLKMODE0 pins, with boot sources including HPI or 8/16/32-bit ROM.

Key Specifications

Pinout & Package

The TMS320C6713BZDP300 uses a 272-ball ZDP BGA package with 1.0-mm ball pitch and an exposed thermal pad. Pin functions follow TI's standardized C67x ball map, with dedicated power (CVDD/DVDD/VSS), clock (CLKIN/CLKOUT2/CLKOUT3/ECLKIN/ECLKOUT), and peripheral signal groups (McASP, McBSP, EMIF, HPI, I2C, GPIO).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar floating-point DSP applications.

Compared with TMS320C6713BGDP300, the ZDP variant offers superior thermal resistance due to enhanced PowerPAD construction, while TMS320C6748BZWT trades McASP DIT capability for ARM integration - making TMS320C6713BZDP300 uniquely suited for standalone, high-channel-count digital audio endpoint designs.

Availability

TMS320C6713BZDP300 is available at Aetrix Electronics and suitable for professional audio equipment, medical ultrasound systems, industrial voice recognition terminals, and real-time signal analysis instruments requiring stable component supply across extended product lifecycles.

Supply support for TMS320C6713BZDP300 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader headquartered in Dallas, Texas, specializing in analog, embedded processing, and digital signal technologies since 1930.

The TMS320C6713BZDP300 belongs to TI's C6000 DSP platform, designed specifically for computationally intensive, real-time floating-point signal processing in audio, communications, and industrial sensing applications.

FAQ

What is the core voltage requirement for TMS320C6713BZDP300 at 300 MHz operation?

The TMS320C6713BZDP300 requires a 1.4-V core supply (CVDD) when operating at 300 MHz, as specified in the "device characteristics" table of SPRS294B. This differs from lower-speed variants (e.g., 225 MHz) which use 1.2-V CVDD. Maintaining precise 1.4-V ±3% regulation is critical to ensure timing closure and prevent functional failure during sustained VLIW instruction dispatch.

Does TMS320C6713BZDP300 support S/PDIF output without external components?

Yes, the TMS320C6713BZDP300 integrates a Digital Audio Interface Transmitter (DIT) that natively supports S/PDIF, IEC60958-1, AES-3, and CP-430 encoding. When configured via McASP registers, it generates fully compliant serial output on up to 16 pins using internal channel status and user data RAM - eliminating need for external S/PDIF encoder ICs in professional audio endpoints.

How many McASP serial data pins does TMS320C6713BZDP300 provide, and how are they allocated?

The TMS320C6713BZDP300 provides 16 McASP serial data pins: eight per McASP module (McASP0 and McASP1). Each pin is individually assignable to either of two independent clock zones (TX or RX), enabling flexible TDM stream routing - for example, assigning four pins to 8-slot I²S input and four to 32-slot S/PDIF output within the same McASP instance.

What boot modes are supported by TMS320C6713BZDP300, and how are they selected?

TMS320C6713BZDP300 supports HPI boot and 8-/16-/32-bit asynchronous ROM boot. Selection is controlled at reset by the HD[4:3], HD8, HD12, and CLKMODE0 pins. For example, HD[4:3] = 00 configures 32-bit ROM boot, while HD[4:3] = 10 selects HPI mode. All configurations require proper pull-up/pull-down biasing per Table 22 in SPRS294B to avoid undefined startup behavior.

Is the TMS320C6713BZDP300 pin-compatible with other C6713B variants such as the PYP QFP package?

No, the TMS320C6713BZDP300 is not pin-compatible with the PYP 208-pin PowerPAD QFP variant. The ZDP uses a 272-ball BGA footprint with distinct ball assignments (e.g., McASP signals on E19, F18, G18), while PYP maps equivalent functions to different pin numbers (e.g., McASP on pins 133–140). PCB layout and signal routing must be redesigned when migrating between ZDP and PYP packages.